mirror of
https://github.com/yuzu-emu/breakpad.git
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Add asm and machine headers
Adds asm/ and machine/ directories to src/common/android/include. This is necessary because some required files for MIPS were removed in newer Android NDK versions, which broke Breakpad compilation. Bug: 771171 Change-Id: Ie6a079b6b8130b549ebc6d0bc4aef0e47e7bd6c2 Reviewed-on: https://chromium-review.googlesource.com/835282 Reviewed-by: Mark Mentovai <mark@chromium.org>
This commit is contained in:
bsheedy
Mark Mentovai
parent
9bcfabcaa7
commit
4a02ec0303
@ -230,16 +230,13 @@ breakpad_getcontext:
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#elif defined(__mips__)
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// This implementation is inspired by implementation of getcontext in glibc.
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#include <asm-mips/asm.h>
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#include <asm-mips/regdef.h>
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#if _MIPS_SIM == _ABIO32
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#include <asm/asm.h>
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#include <asm/regdef.h>
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#include <asm/fpregdef.h>
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#else
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#include <machine/asm.h>
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#include <machine/regdef.h>
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#include <asm-mips/fpregdef.h>
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#endif
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// from asm/asm.h
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// from asm-mips/asm.h
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#if _MIPS_SIM == _ABIO32
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#define ALSZ 7
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#define ALMASK ~7
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9
src/common/android/include/asm-mips/README.md
Normal file
9
src/common/android/include/asm-mips/README.md
Normal file
@ -0,0 +1,9 @@
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# asm-mips
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The files in this directory are almost direct copies from Android NDK r12, with
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the exception of changing the include guards to Breakpad ones. They are copied
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from the MIPS asm/ directory, but are meant to be used as replacements for both
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asm/ and machine/ includes since the files in each are largely duplicates.
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Some MIPS asm/ and all machine/ headers were removed in the move to unified NDK
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headers, so Breakpad fails to compile on newer NDK versions without these files.
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270
src/common/android/include/asm-mips/asm.h
Normal file
270
src/common/android/include/asm-mips/asm.h
Normal file
@ -0,0 +1,270 @@
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#ifndef GOOGLE_BREAKPAD_COMMON_ANDROID_INCLUDE_ASM_MIPS_ASM_H
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#define GOOGLE_BREAKPAD_COMMON_ANDROID_INCLUDE_ASM_MIPS_ASM_H
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#if defined(__has_include_next) && __has_include_next(<asm/asm.h>)
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#include_next <asm/asm.h>
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#else
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
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*** structures, and macros generated from the original header, and thus,
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*** contains no copyrightable information.
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***
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*** To edit the content of this header, modify the corresponding
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*** source file (e.g. under external/kernel-headers/original/) then
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*** run bionic/libc/kernel/tools/update_all.py
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***
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*** Any manual change here will be lost the next time this script will
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#include <asm/sgidefs.h>
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#ifndef CAT
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifdef __STDC__
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#define __CAT(str1, str2) str1##str2
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#else
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#define __CAT(str1, str2) str1 str2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#define CAT(str1, str2) __CAT(str1, str2)
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#endif
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#ifdef __PIC__
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define CPRESTORE(register) .cprestore register
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#define CPADD(register) .cpadd register
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#define CPLOAD(register) .cpload register
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#else
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define CPRESTORE(register)
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#define CPADD(register)
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#define CPLOAD(register)
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define LEAF(symbol) .globl symbol; .align 2; .type symbol, @function; .ent symbol, 0; symbol: .frame sp, 0, ra
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#define NESTED(symbol, framesize, rpc) .globl symbol; .align 2; .type symbol, @function; .ent symbol, 0; symbol: .frame sp, framesize, rpc
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#define END(function) .end function; .size function, .-function
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#define EXPORT(symbol) .globl symbol; symbol:
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define FEXPORT(symbol) .globl symbol; .type symbol, @function; symbol:
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#define ABS(symbol,value) .globl symbol; symbol = value
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#define PANIC(msg) .set push; .set reorder; PTR_LA a0, 8f; jal panic; 9: b 9b; .set pop; TEXT(msg)
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#define PRINT(string)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define TEXT(msg) .pushsection .data; 8: .asciiz msg; .popsection;
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#define TTABLE(string) .pushsection .text; .word 1f; .popsection .pushsection .data; 1: .asciiz string; .popsection
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#define PREF(hint, addr)
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#define PREFX(hint, addr)
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#if _MIPS_ISA == _MIPS_ISA_MIPS1
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#define MOVN(rd, rs, rt) .set push; .set reorder; beqz rt, 9f; move rd, rs; .set pop; 9:
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#define MOVZ(rd, rs, rt) .set push; .set reorder; bnez rt, 9f; move rd, rs; .set pop; 9:
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#if _MIPS_ISA == _MIPS_ISA_MIPS2 || _MIPS_ISA == _MIPS_ISA_MIPS3
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#define MOVN(rd, rs, rt) .set push; .set noreorder; bnezl rt, 9f; move rd, rs; .set pop; 9:
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#define MOVZ(rd, rs, rt) .set push; .set noreorder; beqzl rt, 9f; move rd, rs; .set pop; 9:
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#if _MIPS_ISA == _MIPS_ISA_MIPS4 || _MIPS_ISA == _MIPS_ISA_MIPS5 || _MIPS_ISA == _MIPS_ISA_MIPS32 || _MIPS_ISA == _MIPS_ISA_MIPS64
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#define MOVN(rd, rs, rt) movn rd, rs, rt
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#define MOVZ(rd, rs, rt) movz rd, rs, rt
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#if _MIPS_SIM == _MIPS_SIM_ABI32
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#define ALSZ 7
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#define ALMASK ~7
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#if _MIPS_SIM == _MIPS_SIM_NABI32 || _MIPS_SIM == _MIPS_SIM_ABI64
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#define ALSZ 15
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#define ALMASK ~15
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#endif
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#ifdef __mips64
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#define SZREG 8
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#else
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#define SZREG 4
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#if _MIPS_SIM == _MIPS_SIM_ABI32
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#define REG_S sw
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#define REG_L lw
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define REG_SUBU subu
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#define REG_ADDU addu
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#endif
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#if _MIPS_SIM == _MIPS_SIM_NABI32 || _MIPS_SIM == _MIPS_SIM_ABI64
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define REG_S sd
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#define REG_L ld
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#define REG_SUBU dsubu
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#define REG_ADDU daddu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#if _MIPS_SZINT == 32
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#define INT_ADD add
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#define INT_ADDU addu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define INT_ADDI addi
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#define INT_ADDIU addiu
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#define INT_SUB sub
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#define INT_SUBU subu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define INT_L lw
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#define INT_S sw
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#define INT_SLL sll
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#define INT_SLLV sllv
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define INT_SRL srl
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#define INT_SRLV srlv
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#define INT_SRA sra
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#define INT_SRAV srav
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#if _MIPS_SZINT == 64
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#define INT_ADD dadd
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#define INT_ADDU daddu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define INT_ADDI daddi
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#define INT_ADDIU daddiu
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#define INT_SUB dsub
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#define INT_SUBU dsubu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define INT_L ld
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#define INT_S sd
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#define INT_SLL dsll
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#define INT_SLLV dsllv
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define INT_SRL dsrl
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#define INT_SRLV dsrlv
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#define INT_SRA dsra
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#define INT_SRAV dsrav
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#if _MIPS_SZLONG == 32
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#define LONG_ADD add
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#define LONG_ADDU addu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define LONG_ADDI addi
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#define LONG_ADDIU addiu
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#define LONG_SUB sub
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#define LONG_SUBU subu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define LONG_L lw
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#define LONG_S sw
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#define LONG_SLL sll
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#define LONG_SLLV sllv
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define LONG_SRL srl
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#define LONG_SRLV srlv
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#define LONG_SRA sra
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#define LONG_SRAV srav
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define LONG .word
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#define LONGSIZE 4
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#define LONGMASK 3
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#define LONGLOG 2
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#if _MIPS_SZLONG == 64
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#define LONG_ADD dadd
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#define LONG_ADDU daddu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define LONG_ADDI daddi
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#define LONG_ADDIU daddiu
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#define LONG_SUB dsub
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#define LONG_SUBU dsubu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define LONG_L ld
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#define LONG_S sd
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#define LONG_SLL dsll
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#define LONG_SLLV dsllv
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define LONG_SRL dsrl
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#define LONG_SRLV dsrlv
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#define LONG_SRA dsra
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#define LONG_SRAV dsrav
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define LONG .dword
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#define LONGSIZE 8
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#define LONGMASK 7
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#define LONGLOG 3
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#if _MIPS_SZPTR == 32
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#define PTR_ADD add
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#define PTR_ADDU addu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTR_ADDI addi
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#define PTR_ADDIU addiu
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#define PTR_SUB sub
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#define PTR_SUBU subu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTR_L lw
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#define PTR_S sw
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#define PTR_LA la
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#define PTR_LI li
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTR_SLL sll
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#define PTR_SLLV sllv
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#define PTR_SRL srl
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#define PTR_SRLV srlv
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTR_SRA sra
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#define PTR_SRAV srav
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#define PTR_SCALESHIFT 2
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#define PTR .word
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTRSIZE 4
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#define PTRLOG 2
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#endif
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#if _MIPS_SZPTR == 64
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTR_ADD dadd
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#define PTR_ADDU daddu
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#define PTR_ADDI daddi
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#define PTR_ADDIU daddiu
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTR_SUB dsub
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#define PTR_SUBU dsubu
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#define PTR_L ld
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#define PTR_S sd
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTR_LA dla
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#define PTR_LI dli
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#define PTR_SLL dsll
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#define PTR_SLLV dsllv
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTR_SRL dsrl
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#define PTR_SRLV dsrlv
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#define PTR_SRA dsra
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#define PTR_SRAV dsrav
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define PTR_SCALESHIFT 3
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#define PTR .dword
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#define PTRSIZE 8
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#define PTRLOG 3
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#if _MIPS_SIM == _MIPS_SIM_ABI32
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#define MFC0 mfc0
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#define MTC0 mtc0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#if _MIPS_SIM == _MIPS_SIM_NABI32 || _MIPS_SIM == _MIPS_SIM_ABI64
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#define MFC0 dmfc0
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#define MTC0 dmtc0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#endif
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#define SSNOP sll zero, zero, 1
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#define R10KCBARRIER(addr)
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#endif // defined(__has_include_next) && __has_include_next(<asm/asm.h>)
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#endif // GOOGLE_BREAKPAD_COMMON_ANDROID_INCLUDE_ASM_MIPS_ASM_H
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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117
src/common/android/include/asm-mips/fpregdef.h
Normal file
117
src/common/android/include/asm-mips/fpregdef.h
Normal file
@ -0,0 +1,117 @@
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#ifndef GOOGLE_BREAKPAD_COMMON_ANDROID_INCLUDE_ASM_MIPS_FPREGDEF_H
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#define GOOGLE_BREAKPAD_COMMON_ANDROID_INCLUDE_ASM_MIPS_FPREGDEF_H
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#if defined(__has_include_next) && __has_include_next(<asm/fpregdef.h>)
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#include_next <asm/fpregdef.h>
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#else
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/****************************************************************************
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****************************************************************************
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***
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*** This header was automatically generated from a Linux kernel header
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*** of the same name, to make information necessary for userspace to
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*** call into the kernel available to libc. It contains only constants,
|
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*** structures, and macros generated from the original header, and thus,
|
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*** contains no copyrightable information.
|
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***
|
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*** To edit the content of this header, modify the corresponding
|
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*** source file (e.g. under external/kernel-headers/original/) then
|
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*** run bionic/libc/kernel/tools/update_all.py
|
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***
|
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*** Any manual change here will be lost the next time this script will
|
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*** be run. You've been warned!
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***
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****************************************************************************
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****************************************************************************/
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#include <asm/sgidefs.h>
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#if _MIPS_SIM == _MIPS_SIM_ABI32
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define fv0 $f0
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#define fv0f $f1
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#define fv1 $f2
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#define fv1f $f3
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define fa0 $f12
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#define fa0f $f13
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#define fa1 $f14
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#define fa1f $f15
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define ft0 $f4
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#define ft0f $f5
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#define ft1 $f6
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#define ft1f $f7
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define ft2 $f8
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#define ft2f $f9
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#define ft3 $f10
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#define ft3f $f11
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define ft4 $f16
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#define ft4f $f17
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#define ft5 $f18
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#define ft5f $f19
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define fs0 $f20
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#define fs0f $f21
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#define fs1 $f22
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#define fs1f $f23
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define fs2 $f24
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#define fs2f $f25
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#define fs3 $f26
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#define fs3f $f27
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define fs4 $f28
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#define fs4f $f29
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#define fs5 $f30
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#define fs5f $f31
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
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#define fcr31 $31
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#endif
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#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
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#define fv0 $f0
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/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define fv1 $f2
|
||||
#define fa0 $f12
|
||||
#define fa1 $f13
|
||||
#define fa2 $f14
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define fa3 $f15
|
||||
#define fa4 $f16
|
||||
#define fa5 $f17
|
||||
#define fa6 $f18
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define fa7 $f19
|
||||
#define ft0 $f4
|
||||
#define ft1 $f5
|
||||
#define ft2 $f6
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define ft3 $f7
|
||||
#define ft4 $f8
|
||||
#define ft5 $f9
|
||||
#define ft6 $f10
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define ft7 $f11
|
||||
#define ft8 $f20
|
||||
#define ft9 $f21
|
||||
#define ft10 $f22
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define ft11 $f23
|
||||
#define ft12 $f1
|
||||
#define ft13 $f3
|
||||
#define fs0 $f24
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define fs1 $f25
|
||||
#define fs2 $f26
|
||||
#define fs3 $f27
|
||||
#define fs4 $f28
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define fs5 $f29
|
||||
#define fs6 $f30
|
||||
#define fs7 $f31
|
||||
#define fcr31 $31
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#endif
|
||||
#endif // defined(__has_include_next) && __has_include_next(<asm/fpregdef.h>)
|
||||
#endif // GOOGLE_BREAKPAD_COMMON_ANDROID_INCLUDE_ASM_MIPS_FPREGDEF_H
|
||||
125
src/common/android/include/asm-mips/regdef.h
Normal file
125
src/common/android/include/asm-mips/regdef.h
Normal file
@ -0,0 +1,125 @@
|
||||
#ifndef GOOGLE_BREAKPAD_COMMON_ANDROID_INCLUDE_ASM_MIPS_REGDEF_H
|
||||
#define GOOGLE_BREAKPAD_COMMON_ANDROID_INCLUDE_ASM_MIPS_REGDEF_H
|
||||
|
||||
#if defined(__has_include_next) && __has_include_next(<asm/regdef.h>)
|
||||
#include_next <asm/regdef.h>
|
||||
#else
|
||||
|
||||
/****************************************************************************
|
||||
****************************************************************************
|
||||
***
|
||||
*** This header was automatically generated from a Linux kernel header
|
||||
*** of the same name, to make information necessary for userspace to
|
||||
*** call into the kernel available to libc. It contains only constants,
|
||||
*** structures, and macros generated from the original header, and thus,
|
||||
*** contains no copyrightable information.
|
||||
***
|
||||
*** To edit the content of this header, modify the corresponding
|
||||
*** source file (e.g. under external/kernel-headers/original/) then
|
||||
*** run bionic/libc/kernel/tools/update_all.py
|
||||
***
|
||||
*** Any manual change here will be lost the next time this script will
|
||||
*** be run. You've been warned!
|
||||
***
|
||||
****************************************************************************
|
||||
****************************************************************************/
|
||||
|
||||
#include <asm/sgidefs.h>
|
||||
#if _MIPS_SIM == _MIPS_SIM_ABI32
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define zero $0
|
||||
#define AT $1
|
||||
#define v0 $2
|
||||
#define v1 $3
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define a0 $4
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define t0 $8
|
||||
#define t1 $9
|
||||
#define t2 $10
|
||||
#define t3 $11
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define t4 $12
|
||||
#define t5 $13
|
||||
#define t6 $14
|
||||
#define t7 $15
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define s0 $16
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define t8 $24
|
||||
#define t9 $25
|
||||
#define jp $25
|
||||
#define k0 $26
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define k1 $27
|
||||
#define gp $28
|
||||
#define sp $29
|
||||
#define fp $30
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define s8 $30
|
||||
#define ra $31
|
||||
#endif
|
||||
#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define zero $0
|
||||
#define AT $at
|
||||
#define v0 $2
|
||||
#define v1 $3
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define a0 $4
|
||||
#define a1 $5
|
||||
#define a2 $6
|
||||
#define a3 $7
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define a4 $8
|
||||
#define ta0 $8
|
||||
#define a5 $9
|
||||
#define ta1 $9
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define a6 $10
|
||||
#define ta2 $10
|
||||
#define a7 $11
|
||||
#define ta3 $11
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define t0 $12
|
||||
#define t1 $13
|
||||
#define t2 $14
|
||||
#define t3 $15
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define s0 $16
|
||||
#define s1 $17
|
||||
#define s2 $18
|
||||
#define s3 $19
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define s4 $20
|
||||
#define s5 $21
|
||||
#define s6 $22
|
||||
#define s7 $23
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define t8 $24
|
||||
#define t9 $25
|
||||
#define jp $25
|
||||
#define k0 $26
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define k1 $27
|
||||
#define gp $28
|
||||
#define sp $29
|
||||
#define fp $30
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
#define s8 $30
|
||||
#define ra $31
|
||||
#endif
|
||||
#endif // defined(__has_include_next) && __has_include_next(<asm/regdef.h>)
|
||||
#endif // GOOGLE_BREAKPAD_COMMON_ANDROID_INCLUDE_ASM_MIPS_REGDEF_H
|
||||
/* WARNING: DO NOT EDIT, AUTO-GENERATED CODE - SEE TOP FOR INSTRUCTIONS */
|
||||
Loading…
Reference in New Issue
Block a user