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Add RISC-V register names

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RISC-V register names are needed in order to load DWARF call frame
information.

Bug: fuchsia:124084
Change-Id: I2791b3a38ea35ddc2bb293f60f75dcc86338e354
Reviewed-on: https://chromium-review.googlesource.com/c/breakpad/breakpad/+/4376827
Reviewed-by: Mike Frysinger <vapier@chromium.org>
This commit is contained in:
Thomas Gales 2023-03-28 21:14:44 +00:00 committed by Mike Frysinger
parent b0dc1f3529
commit 4d8bb33976
4 changed files with 41 additions and 0 deletions
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23
src/common/dwarf_cfi_to_module.cc
View File

@ -147,6 +147,29 @@ vector<string> DwarfCFIToModule::RegisterNames::MIPS() {
sizeof(kRegisterNames) / sizeof(kRegisterNames[0])); sizeof(kRegisterNames) / sizeof(kRegisterNames[0]));
} }
vector<string> DwarfCFIToModule::RegisterNames::RISCV() {
static const char *const names[] = {
"x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
"x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
"x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "",
"v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7",
"v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15",
"v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23",
"v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31"
};
return MakeVector(names, sizeof(names) / sizeof(names[0]));
}
bool DwarfCFIToModule::Entry(size_t offset, uint64_t address, uint64_t length, bool DwarfCFIToModule::Entry(size_t offset, uint64_t address, uint64_t length,
uint8_t version, const string& augmentation, uint8_t version, const string& augmentation,
unsigned return_address) { unsigned return_address) {

3
src/common/dwarf_cfi_to_module.h
View File

@ -114,6 +114,9 @@ class DwarfCFIToModule: public CallFrameInfo::Handler {
// MIPS. // MIPS.
static vector<string> MIPS(); static vector<string> MIPS();
// RISC-V.
static vector<string> RISCV();
private: private:
// Given STRINGS, an array of C strings with SIZE elements, return an // Given STRINGS, an array of C strings with SIZE elements, return an
// equivalent vector<string>. // equivalent vector<string>.

12
src/common/dwarf_cfi_to_module_unittest.cc
View File

@ -307,3 +307,15 @@ TEST(RegisterNames, X86_64) {
EXPECT_EQ("$rsp", names[7]); EXPECT_EQ("$rsp", names[7]);
EXPECT_EQ("$rip", names[16]); EXPECT_EQ("$rip", names[16]);
} }
TEST(RegisterNames, RISCV) {
vector<string> names = DwarfCFIToModule::RegisterNames::RISCV();
EXPECT_EQ("x0", names[0]);
EXPECT_EQ("x31", names[31]);
EXPECT_EQ("f0", names[32]);
EXPECT_EQ("f31", names[63]);
EXPECT_EQ("v0", names[96]);
EXPECT_EQ("v31", names[127]);
}

3
src/common/linux/dump_symbols.cc
View File

@ -449,6 +449,9 @@ bool DwarfCFIRegisterNames(const typename ElfClass::Ehdr* elf_header,
case EM_X86_64: case EM_X86_64:
*register_names = DwarfCFIToModule::RegisterNames::X86_64(); *register_names = DwarfCFIToModule::RegisterNames::X86_64();
return true; return true;
case EM_RISCV:
*register_names = DwarfCFIToModule::RegisterNames::RISCV();
return true;
default: default:
return false; return false;
} }