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unicorn/qemu/target-i386/cpu.c

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import
2015-08-21 09:04:50 +02:00
/*
* i386 CPUID helper functions
*
* Copyright (c) 2003 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
x86: Clean up includes Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Backports commit b6a0aa053711e27e1a7825c1fca662beb05bee6f from qemu
2018-02-19 06:56:22 +01:00
#include "qemu/osdep.h"
util: move declarations out of qemu-common.h Move declarations out of qemu-common.h for functions declared in utils/ files: e.g. include/qemu/path.h for utils/path.c. Move inline functions out of qemu-common.h and into new files (e.g. include/qemu/bcd.h) Backports commit f348b6d1a53e5271cf1c9f9acc4646b4b98c1771 from qemu
2018-02-22 15:24:12 +01:00
#include "qemu/cutils.h"
include/qemu/osdep.h: Don't include qapi/error.h Commit 57cb38b included qapi/error.h into qemu/osdep.h to get the Error typedef. Since then, we've moved to include qemu/osdep.h everywhere. Its file comment explains: "To avoid getting into possible circular include dependencies, this file should not include any other QEMU headers, with the exceptions of config-host.h, compiler.h, os-posix.h and os-win32.h, all of which are doing a similar job to this file and are under similar constraints." qapi/error.h doesn't do a similar job, and it doesn't adhere to similar constraints: it includes qapi-types.h. That's in excess of 100KiB of crap most .c files don't actually need. Add the typedef to qemu/typedefs.h, and include that instead of qapi/error.h. Include qapi/error.h in .c files that need it and don't get it now. Include qapi-types.h in qom/object.h for uint16List. Update scripts/clean-includes accordingly. Update it further to match reality: replace config.h by config-target.h, add sysemu/os-posix.h, sysemu/os-win32.h. Update the list of includes in the qemu/osdep.h comment quoted above similarly. This reduces the number of objects depending on qapi/error.h from "all of them" to less than a third. Unfortunately, the number depending on qapi-types.h shrinks only a little. More work is needed for that one. Backports commit da34e65cb4025728566d6504a99916f6e7e1dd6a from qemu
2018-02-22 05:05:15 +01:00
#include "qapi/error.h"
platform.h move #3
2017-01-20 14:13:21 +01:00
#include "unicorn/platform.h"
import
2015-08-21 09:04:50 +02:00
#include "cpu.h"
cpu: move exec-all.h inclusion out of cpu.h exec-all.h contains TCG-specific definitions. It is not needed outside TCG-specific files such as translate.c, exec.c or *helper.c. One generic function had snuck into include/exec/exec-all.h; move it to include/qom/cpu.h. Backports commit 63c915526d6a54a95919ebece83fa9ca631b2508 from qemu
2018-02-24 08:26:26 +01:00
#include "exec/exec-all.h"
import
2015-08-21 09:04:50 +02:00
#include "sysemu/cpus.h"
target-i386: Allow physical address bits to be set Currently QEMU sets the x86 number of physical address bits to the magic number 40. This is only correct on some small AMD systems; Intel systems tend to have 36, 39, 46 bits, and large AMD systems tend to have 48. Having the value different from your actual hardware is detectable by the guest and in principal can cause problems; The current limit of 40 stops TB VMs being created by those lucky enough to have that much. This patch lets you set the physical bits by a cpu property but defaults to the same 40bits which matches TCGs setup. I've removed the ancient warning about the 42 bit limit in exec.c; I can't find that limit in there and no one else seems to know where it is. We use a magic value of 0 as the property default so that we can later distinguish between the default and a user set value. Backports commit af45907a132857cfd47acc998bf5f7c26cd13071 from qemu
2018-02-26 02:25:32 +01:00
#include "sysemu/kvm.h"
import
2015-08-21 09:04:50 +02:00
#include "qapi/qmp/qerror.h"
#include "qapi-types.h"
#include "qapi-visit.h"
#include "qapi/visitor.h"
#include "hw/hw.h"
#include "sysemu/sysemu.h"
target-i386: Implement CPUID[0xB] (Extended Topology Enumeration) I looked at a dozen Intel CPU that have this CPUID and all of them always had Core offset as 1 (a wasted bit when hyperthreading is disabled) and Package offset at least 4 (wasted bits at <= 4 cores). QEMU uses more compact IDs and it doesn't make much sense to change it now. I keep the SMT and Core sub-leaves even if there is just one thread/core; it makes the code simpler and there should be no harm. Backports commit 5232d00a041c8f3628b3532ef35d703a1f0dac19 from qemu
2018-02-25 00:29:20 +01:00
#include "topology.h"
import
2015-08-21 09:04:50 +02:00
#include "hw/cpu/icc_bus.h"
#ifndef CONFIG_USER_ONLY
target-i386: create a separate AddressSpace for each CPU Different CPUs can be in SMM or not at the same time, thus they will see different things where the chipset places SMRAM. Backports commit 2001d0cd6d55e5efa9956fa8ff8b89034d6a4329 from qemu
2018-02-13 18:34:42 +01:00
#include "exec/address-spaces.h"
import
2015-08-21 09:04:50 +02:00
#include "hw/i386/apic_internal.h"
#endif
/* Cache topology CPUID constants: */
/* CPUID Leaf 2 Descriptors */
#define CPUID_2_L1D_32KB_8WAY_64B 0x2c
#define CPUID_2_L1I_32KB_8WAY_64B 0x30
#define CPUID_2_L2_2MB_8WAY_64B 0x7d
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Backports commit 14c985cffa6cb177fc01a163d8bcf227c104718c from qemu
2018-02-26 05:16:03 +01:00
#define CPUID_2_L3_16MB_16WAY_64B 0x4d
import
2015-08-21 09:04:50 +02:00
/* CPUID Leaf 4 constants: */
/* EAX: */
#define CPUID_4_TYPE_DCACHE 1
#define CPUID_4_TYPE_ICACHE 2
#define CPUID_4_TYPE_UNIFIED 3
#define CPUID_4_LEVEL(l) ((l) << 5)
#define CPUID_4_SELF_INIT_LEVEL (1 << 8)
#define CPUID_4_FULLY_ASSOC (1 << 9)
/* EDX: */
#define CPUID_4_NO_INVD_SHARING (1 << 0)
#define CPUID_4_INCLUSIVE (1 << 1)
#define CPUID_4_COMPLEX_IDX (1 << 2)
#define ASSOC_FULL 0xFF
/* AMD associativity encoding used on CPUID Leaf 0x80000006: */
#define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
a == 2 ? 0x2 : \
a == 4 ? 0x4 : \
a == 8 ? 0x6 : \
a == 16 ? 0x8 : \
a == 32 ? 0xA : \
a == 48 ? 0xB : \
a == 64 ? 0xC : \
a == 96 ? 0xD : \
a == 128 ? 0xE : \
a == ASSOC_FULL ? 0xF : \
0 /* invalid value */)
/* Definitions of the hardcoded cache entries we expose: */
/* L1 data cache: */
#define L1D_LINE_SIZE 64
#define L1D_ASSOCIATIVITY 8
#define L1D_SETS 64
#define L1D_PARTITIONS 1
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
#define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
#define L1D_LINES_PER_TAG 1
#define L1D_SIZE_KB_AMD 64
#define L1D_ASSOCIATIVITY_AMD 2
/* L1 instruction cache: */
#define L1I_LINE_SIZE 64
#define L1I_ASSOCIATIVITY 8
#define L1I_SETS 64
#define L1I_PARTITIONS 1
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
#define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
#define L1I_LINES_PER_TAG 1
#define L1I_SIZE_KB_AMD 64
#define L1I_ASSOCIATIVITY_AMD 2
/* Level 2 unified cache: */
#define L2_LINE_SIZE 64
#define L2_ASSOCIATIVITY 16
#define L2_SETS 4096
#define L2_PARTITIONS 1
/* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
#define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
#define L2_LINES_PER_TAG 1
#define L2_SIZE_KB_AMD 512
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Backports commit 14c985cffa6cb177fc01a163d8bcf227c104718c from qemu
2018-02-26 05:16:03 +01:00
/* Level 3 unified cache: */
import
2015-08-21 09:04:50 +02:00
#define L3_SIZE_KB 0 /* disabled */
#define L3_ASSOCIATIVITY 0 /* disabled */
#define L3_LINES_PER_TAG 0 /* disabled */
#define L3_LINE_SIZE 0 /* disabled */
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Backports commit 14c985cffa6cb177fc01a163d8bcf227c104718c from qemu
2018-02-26 05:16:03 +01:00
#define L3_N_LINE_SIZE 64
#define L3_N_ASSOCIATIVITY 16
#define L3_N_SETS 16384
#define L3_N_PARTITIONS 1
#define L3_N_DESCRIPTOR CPUID_2_L3_16MB_16WAY_64B
#define L3_N_LINES_PER_TAG 1
#define L3_N_SIZE_KB_AMD 16384
import
2015-08-21 09:04:50 +02:00
/* TLB definitions: */
#define L1_DTLB_2M_ASSOC 1
#define L1_DTLB_2M_ENTRIES 255
#define L1_DTLB_4K_ASSOC 1
#define L1_DTLB_4K_ENTRIES 255
#define L1_ITLB_2M_ASSOC 1
#define L1_ITLB_2M_ENTRIES 255
#define L1_ITLB_4K_ASSOC 1
#define L1_ITLB_4K_ENTRIES 255
#define L2_DTLB_2M_ASSOC 0 /* disabled */
#define L2_DTLB_2M_ENTRIES 0 /* disabled */
#define L2_DTLB_4K_ASSOC 4
#define L2_DTLB_4K_ENTRIES 512
#define L2_ITLB_2M_ASSOC 0 /* disabled */
#define L2_ITLB_2M_ENTRIES 0 /* disabled */
#define L2_ITLB_4K_ASSOC 4
#define L2_ITLB_4K_ENTRIES 512
void x86_cpu_register_types(void *);
static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
uint32_t vendor2, uint32_t vendor3)
{
int i;
for (i = 0; i < 4; i++) {
dst[i] = vendor1 >> (8 * i);
dst[i + 4] = vendor2 >> (8 * i);
dst[i + 8] = vendor3 >> (8 * i);
}
dst[CPUID_VENDOR_SZ] = '\0';
}
#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
CPUID_PSE36 | CPUID_FXSR)
#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
CPUID_PAE | CPUID_SEP | CPUID_APIC)
#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
target-i386: Add DE to TCG_FEATURES Now DE is supported by TCG so it can be enabled in CPUID bits. Backports commit b6c5a6f021f485fc36bca678b2c867e9b6783924 from qemu
2018-02-16 22:30:26 +01:00
CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS | CPUID_DE)
import
2015-08-21 09:04:50 +02:00
/* partly implemented:
CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
/* missing:
CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
target-i386: Add XSAVE extension This includes XSAVE, XRSTOR, XGETBV, XSETBV, which are all related, as well as the associate cpuid bits. Backports commit 19dc85dba23c0db1ca932c62e453c37e00761628 from qemu
2018-02-20 18:46:01 +01:00
CPUID_EXT_XSAVE | /* CPUID_EXT_OSXSAVE is dynamic */ \
import
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CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
/* missing:
CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
target-i386: Add XSAVE extension This includes XSAVE, XRSTOR, XGETBV, XSETBV, which are all related, as well as the associate cpuid bits. Backports commit 19dc85dba23c0db1ca932c62e453c37e00761628 from qemu
2018-02-20 18:46:01 +01:00
CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_AVX,
CPUID_EXT_F16C, CPUID_EXT_RDRAND */
import
2015-08-21 09:04:50 +02:00
#ifdef TARGET_X86_64
#define TCG_EXT2_X86_64_FEATURES (CPUID_EXT2_SYSCALL | CPUID_EXT2_LM)
#else
#define TCG_EXT2_X86_64_FEATURES 0
#endif
#define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB | \
TCG_EXT2_X86_64_FEATURES)
#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
#define TCG_EXT4_FEATURES 0
#define TCG_SVM_FEATURES 0
#define TCG_KVM_FEATURES 0
#define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \
target-i386: Add clflushopt/clwb/pcommit to TCG_7_0_EBX_FEATURES Now these instructions are handled by TCG and can be added to the TCG_7_0_EBX_FEATURES macro. Backports commit 0c47242b519a224279f13c685aa6e79347f97b85 from qemu
2018-02-17 23:26:43 +01:00
CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \
CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \
target-i386: TCG can support CPUID.07H:EBX.erms ERMS just says "rep movsb" and "rep stosb" are fast. It does not imply any new instruction, so we can support it easily. Backports commit 7eb24386dbfb0b66464c7f856c1074c606efccda from qemu
2018-02-25 08:28:52 +01:00
CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
CPUID_7_0_EBX_ERMS)
import
2015-08-21 09:04:50 +02:00
/* missing:
target-i386: Implement FSGSBASE Backports commit 07929f2ab2ab9c9e01d4ae79f48f2b2476b715c8 from qemu
2018-02-20 20:42:19 +01:00
CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
target-i386: TCG can support CPUID.07H:EBX.erms ERMS just says "rep movsb" and "rep stosb" are fast. It does not imply any new instruction, so we can support it easily. Backports commit 7eb24386dbfb0b66464c7f856c1074c606efccda from qemu
2018-02-25 08:28:52 +01:00
CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
import
2015-08-21 09:04:50 +02:00
CPUID_7_0_EBX_RDSEED */
target-i386: implement PKE for TCG Backports commit 0f70ed4759a29ca932af1e9525729f4f455642f8 from qemu
2018-02-22 16:18:48 +01:00
#define TCG_7_0_ECX_FEATURES (CPUID_7_0_ECX_PKU | CPUID_7_0_ECX_OSPKE)
import
2015-08-21 09:04:50 +02:00
#define TCG_APM_FEATURES 0
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
#define TCG_6_EAX_FEATURES CPUID_6_EAX_ARAT
import
2015-08-21 09:04:50 +02:00
target-i386: Implement XSAVEOPT Backports commit c9cfe8f9fb21f086e24b3a8f7ccd9c06e4d8d9d6 from qemu
2018-02-20 18:52:07 +01:00
#define TCG_XSAVE_FEATURES (CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XGETBV1)
/* missing:
CPUID_XSAVE_XSAVEC, CPUID_XSAVE_XSAVES */
import
2015-08-21 09:04:50 +02:00
typedef struct FeatureWordInfo {
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
/* feature flags names are taken from "Intel Processor Identification and
* the CPUID Instruction" and AMD's "CPUID Specification".
* In cases of disagreement between feature naming conventions,
* aliases may be added.
*/
const char *feat_names[32];
import
2015-08-21 09:04:50 +02:00
uint32_t cpuid_eax; /* Input EAX for CPUID */
bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
uint32_t cpuid_ecx; /* Input ECX value for CPUID */
int cpuid_reg; /* output register (R_* constant) */
uint32_t tcg_features; /* Feature flags supported by TCG */
uint32_t unmigratable_flags; /* Feature flags known to be unmigratable */
} FeatureWordInfo;
static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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// FEAT_1_EDX
{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
"fpu", "vme", "de", "pse",
"tsc", "msr", "pae", "mce",
"cx8", "apic", NULL, "sep",
"mtrr", "pge", "mca", "cmov",
"pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
NULL, "ds" /* Intel dts */, "acpi", "mmx",
"fxsr", "sse", "sse2", "ss",
"ht" /* Intel htt */, "tm", "ia64", "pbe",
},
This code should now build the x86_x64-softmmu part 2.
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1,
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false,0,
R_EDX,
This code should now build the x86_x64-softmmu part 2.
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TCG_FEATURES,
},
// FEAT_1_ECX
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{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
"pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
"ds_cpl", "vmx", "smx", "est",
"tm2", "ssse3", "cid", NULL,
"fma", "cx16", "xtpr", "pdcm",
NULL, "pcid", "dca", "sse4.1|sse4_1",
"sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
"tsc-deadline", "aes", "xsave", "osxsave",
"avx", "f16c", "rdrand", "hypervisor",
},
This code should now build the x86_x64-softmmu part 2.
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1,
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false,0,
R_ECX,
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TCG_EXT_FEATURES,
},
// FEAT_7_0_EBX
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{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
"fsgsbase", "tsc_adjust", NULL, "bmi1",
"hle", "avx2", NULL, "smep",
"bmi2", "erms", "invpcid", "rtm",
NULL, NULL, "mpx", NULL,
"avx512f", "avx512dq", "rdseed", "adx",
"smap", "avx512ifma", "pcommit", "clflushopt",
"clwb", NULL, "avx512pf", "avx512er",
"avx512cd", NULL, "avx512bw", "avx512vl",
},
This code should now build the x86_x64-softmmu part 2.
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7,
true, 0,
R_EBX,
TCG_7_0_EBX_FEATURES,
},
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
NULL, "avx512vbmi", "umip", "pku",
"ospke", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, "rdpid", NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
7,
true, 0,
R_ECX,
TCG_7_0_ECX_FEATURES,
},
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
/* Feature names that are already defined on feature_name[] but
* are set on CPUID[8000_0001].EDX on AMD CPUs don't have their
* names on feat_names below. They are copied automatically
* to features[FEAT_8000_0001_EDX] if and only if CPU vendor is AMD.
*/
This code should now build the x86_x64-softmmu part 2.
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// FEAT_8000_0001_EDX
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{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
NULL /* cx8 */, NULL /* apic */, NULL, "syscall",
NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
"nx|xd", NULL, "mmxext", NULL /* mmx */,
NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb", "rdtscp",
NULL, "lm|i64", "3dnowext", "3dnow",
},
This code should now build the x86_x64-softmmu part 2.
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0x80000001,
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false,0,
R_EDX,
This code should now build the x86_x64-softmmu part 2.
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TCG_EXT2_FEATURES,
},
// FEAT_8000_0001_ECX
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{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
"lahf_lm", "cmp_legacy", "svm", "extapic",
"cr8legacy", "abm", "sse4a", "misalignsse",
"3dnowprefetch", "osvw", "ibs", "xop",
"skinit", "wdt", NULL, "lwp",
"fma4", "tce", NULL, "nodeid_msr",
NULL, "tbm", "topoext", "perfctr_core",
"perfctr_nb", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
This code should now build the x86_x64-softmmu part 2.
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0x80000001,
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false,0,
R_ECX,
This code should now build the x86_x64-softmmu part 2.
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TCG_EXT3_FEATURES,
},
// FEAT_8000_0007_EDX
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{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
"invtsc", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
This code should now build the x86_x64-softmmu part 2.
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0x80000007,
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false,0,
This code should now build the x86_x64-softmmu part 2.
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R_EDX,
TCG_APM_FEATURES,
CPUID_APM_INVTSC,
},
// FEAT_C000_0001_EDX
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{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
NULL, NULL, "xstore", "xstore-en",
NULL, NULL, "xcrypt", "xcrypt-en",
"ace2", "ace2-en", "phe", "phe-en",
"pmm", "pmm-en", NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
This code should now build the x86_x64-softmmu part 2.
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0xC0000001,
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false,0,
R_EDX,
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TCG_EXT4_FEATURES,
},
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// FEAT_KVM
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{{NULL},
/* Unicorn: commented out
{
"kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
"kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
"kvmclock-stable-bit", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
KVM_CPUID_FEATURES,
false, 0,
R_EAX,
TCG_KVM_FEATURES,*/
},
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
NULL /* hv_msr_vp_runtime_access */, NULL /* hv_msr_time_refcount_access */,
NULL /* hv_msr_synic_access */, NULL /* hv_msr_stimer_access */,
NULL /* hv_msr_apic_access */, NULL /* hv_msr_hypercall_access */,
NULL /* hv_vpindex_access */, NULL /* hv_msr_reset_access */,
NULL /* hv_msr_stats_access */, NULL /* hv_reftsc_access */,
NULL /* hv_msr_idle_access */, NULL /* hv_msr_frequency_access */,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
0x40000003,
false, 0,
R_EAX,
},
// FEAT_HYPERV_EBX
{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
NULL /* hv_create_partitions */, NULL /* hv_access_partition_id */,
NULL /* hv_access_memory_pool */, NULL /* hv_adjust_message_buffers */,
NULL /* hv_post_messages */, NULL /* hv_signal_events */,
NULL /* hv_create_port */, NULL /* hv_connect_port */,
NULL /* hv_access_stats */, NULL, NULL, NULL /* hv_debugging */,
NULL /* hv_cpu_power_management */, NULL /* hv_configure_profiler */,
NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
0x40000003,
false, 0,
R_EBX,
},
// FEAT_HYPERV_EDX
{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
NULL /* hv_mwait */, NULL /* hv_guest_debugging */,
NULL /* hv_perf_monitor */, NULL /* hv_cpu_dynamic_part */,
NULL /* hv_hypercall_params_xmm */, NULL /* hv_guest_idle_state */,
NULL, NULL,
NULL, NULL, NULL /* hv_guest_crash_msr */, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
0x40000003,
false, 0,
R_EDX,
},
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// FEAT_SVM
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
"npt", "lbrv", "svm_lock", "nrip_save",
"tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
NULL, NULL, "pause_filter", NULL,
"pfthreshold", NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
0x8000000A,
false, 0,
R_EDX,
0,
TCG_SVM_FEATURES,
},
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1] These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-14 21:46:12 +01:00
// FEAT_XSAVE
{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
"xsaveopt", "xsavec", "xgetbv1", "xsaves",
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1] These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-14 21:46:12 +01:00
0xd,
true,1,
R_EAX,
0,
target-i386: Implement XSAVEOPT Backports commit c9cfe8f9fb21f086e24b3a8f7ccd9c06e4d8d9d6 from qemu
2018-02-20 18:52:07 +01:00
TCG_XSAVE_FEATURES,
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1] These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-14 21:46:12 +01:00
},
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
// FEAT_ARAT
{
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
{
NULL, NULL, "arat", NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
},
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
6,
false, 0,
R_EAX,
TCG_6_EAX_FEATURES,
}
import
2015-08-21 09:04:50 +02:00
};
typedef struct X86RegisterInfo32 {
/* Name of register */
const char *name;
/* QAPI enum value register */
X86CPURegister32 qapi_enum;
} X86RegisterInfo32;
#define REGISTER(reg) \
This code should now build the x86_x64-softmmu part 2.
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{ #reg, X86_CPU_REGISTER32_##reg }
import
2015-08-21 09:04:50 +02:00
static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
REGISTER(EAX),
REGISTER(ECX),
REGISTER(EDX),
REGISTER(EBX),
REGISTER(ESP),
REGISTER(EBP),
REGISTER(ESI),
REGISTER(EDI),
};
#undef REGISTER
target-i386: Use struct X86XSaveArea in fpu_helper.c This avoids a double hand-full of magic numbers in the xsave and xrstor helper functions. Backports commit 3f32bd21df655e62eb271182a5c63280d631c7b3 from qemu
2018-02-26 09:33:57 +01:00
typedef struct ExtSaveArea {
uint32_t feature, bits;
uint32_t offset, size;
} ExtSaveArea;
static const ExtSaveArea x86_ext_save_areas[] = {
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
// XSTATE_FP_BIT
{
0, 0,
0, 0
},
// XSTATE_SSE_BIT
{
0, 0,
0, 0,
},
// XSTATE_YMM_BIT
{
FEAT_1_ECX, CPUID_EXT_AVX,
target-i386: Use xsave structs for ext_save_area This doesn't introduce any change in the code, as the offsets and struct sizes match what was present in the table. This can be validated by the QEMU_BUILD_BUG_ON lines on target-i386/cpu.h, which ensures the struct sizes and offsets match the existing values in ext_save_area. Backports commit ee1b09f695dcd8532f470e53297473bd3bc88718 from qemu
2018-02-24 09:13:08 +01:00
offsetof(X86XSaveArea, avx_state),
sizeof(XSaveAVX),
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
},
// XSTATE_BNDREGS_BIT
{
FEAT_7_0_EBX, CPUID_7_0_EBX_MPX,
target-i386: Use xsave structs for ext_save_area This doesn't introduce any change in the code, as the offsets and struct sizes match what was present in the table. This can be validated by the QEMU_BUILD_BUG_ON lines on target-i386/cpu.h, which ensures the struct sizes and offsets match the existing values in ext_save_area. Backports commit ee1b09f695dcd8532f470e53297473bd3bc88718 from qemu
2018-02-24 09:13:08 +01:00
offsetof(X86XSaveArea, bndreg_state),
sizeof(XSaveBNDREG),
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
},
// XSTATE_BNDCSR_BIT
{
FEAT_7_0_EBX, CPUID_7_0_EBX_MPX,
target-i386: Use xsave structs for ext_save_area This doesn't introduce any change in the code, as the offsets and struct sizes match what was present in the table. This can be validated by the QEMU_BUILD_BUG_ON lines on target-i386/cpu.h, which ensures the struct sizes and offsets match the existing values in ext_save_area. Backports commit ee1b09f695dcd8532f470e53297473bd3bc88718 from qemu
2018-02-24 09:13:08 +01:00
offsetof(X86XSaveArea, bndcsr_state),
sizeof(XSaveBNDCSR),
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
},
// XSTATE_OPMASK_BIT
{
FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F,
target-i386: Use xsave structs for ext_save_area This doesn't introduce any change in the code, as the offsets and struct sizes match what was present in the table. This can be validated by the QEMU_BUILD_BUG_ON lines on target-i386/cpu.h, which ensures the struct sizes and offsets match the existing values in ext_save_area. Backports commit ee1b09f695dcd8532f470e53297473bd3bc88718 from qemu
2018-02-24 09:13:08 +01:00
offsetof(X86XSaveArea, opmask_state),
sizeof(XSaveOpmask),
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
},
// XSTATE_ZMM_Hi256_BIT
{
FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F,
target-i386: Use xsave structs for ext_save_area This doesn't introduce any change in the code, as the offsets and struct sizes match what was present in the table. This can be validated by the QEMU_BUILD_BUG_ON lines on target-i386/cpu.h, which ensures the struct sizes and offsets match the existing values in ext_save_area. Backports commit ee1b09f695dcd8532f470e53297473bd3bc88718 from qemu
2018-02-24 09:13:08 +01:00
offsetof(X86XSaveArea, zmm_hi256_state),
sizeof(XSaveZMM_Hi256),
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
},
// XSTATE_Hi16_ZMM_BIT
{
FEAT_7_0_EBX, CPUID_7_0_EBX_AVX512F,
target-i386: Use xsave structs for ext_save_area This doesn't introduce any change in the code, as the offsets and struct sizes match what was present in the table. This can be validated by the QEMU_BUILD_BUG_ON lines on target-i386/cpu.h, which ensures the struct sizes and offsets match the existing values in ext_save_area. Backports commit ee1b09f695dcd8532f470e53297473bd3bc88718 from qemu
2018-02-24 09:13:08 +01:00
offsetof(X86XSaveArea, hi16_zmm_state),
sizeof(XSaveHi16_ZMM),
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
},
// XSTATE_PKRU_BIT
{
target-i386: Use xsave structs for ext_save_area This doesn't introduce any change in the code, as the offsets and struct sizes match what was present in the table. This can be validated by the QEMU_BUILD_BUG_ON lines on target-i386/cpu.h, which ensures the struct sizes and offsets match the existing values in ext_save_area. Backports commit ee1b09f695dcd8532f470e53297473bd3bc88718 from qemu
2018-02-24 09:13:08 +01:00
FEAT_7_0_ECX, CPUID_7_0_ECX_PKU,
offsetof(X86XSaveArea, pkru_state),
sizeof(XSavePKRU),
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
},
};
import
2015-08-21 09:04:50 +02:00
const char *get_register_name_32(unsigned int reg)
{
if (reg >= CPU_NB_REGS32) {
return NULL;
}
return x86_reg_info_32[reg].name;
}
This code should now build the x86_x64-softmmu part 2.
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#ifdef _MSC_VER
#include <intrin.h>
#endif
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
/*
* Returns the set of feature flags that are supported and migratable by
* QEMU, for a given FeatureWord.
*/
static uint32_t x86_cpu_get_migratable_flags(FeatureWord w)
{
FeatureWordInfo *wi = &feature_word_info[w];
uint32_t r = 0;
int i;
for (i = 0; i < 32; i++) {
uint32_t f = 1U << i;
/* If the feature name is unknown, it is not supported by QEMU yet */
if (!wi->feat_names[i]) {
continue;
}
/* Skip features known to QEMU, but explicitly marked as unmigratable */
if (wi->unmigratable_flags & f) {
continue;
}
r |= f;
}
return r;
}
import
2015-08-21 09:04:50 +02:00
void host_cpuid(uint32_t function, uint32_t count,
uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
{
uint32_t vec[4];
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
#ifdef _MSC_VER
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
__cpuidex((int*)vec, function, count);
This code should now build the x86_x64-softmmu part 2.
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#else
import
2015-08-21 09:04:50 +02:00
#ifdef __x86_64__
asm volatile("cpuid"
: "=a"(vec[0]), "=b"(vec[1]),
"=c"(vec[2]), "=d"(vec[3])
: "0"(function), "c"(count) : "cc");
#elif defined(__i386__)
asm volatile("pusha \n\t"
"cpuid \n\t"
"mov %%eax, 0(%2) \n\t"
"mov %%ebx, 4(%2) \n\t"
"mov %%ecx, 8(%2) \n\t"
"mov %%edx, 12(%2) \n\t"
"popa"
: : "a"(function), "c"(count), "S"(vec)
: "memory", "cc");
#else
abort();
#endif
This code should now build the x86_x64-softmmu part 2.
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#endif // _MSC_VER
import
2015-08-21 09:04:50 +02:00
if (eax)
*eax = vec[0];
if (ebx)
*ebx = vec[1];
if (ecx)
*ecx = vec[2];
if (edx)
*edx = vec[3];
}
#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
* a substring. ex if !NULL points to the first char after a substring,
* otherwise the string is assumed to sized by a terminating nul.
* Return lexical ordering of *s1:*s2.
*/
static int sstrcmp(const char *s1, const char *e1,
const char *s2, const char *e2)
{
for (;;) {
if (!*s1 || !*s2 || *s1 != *s2)
return (*s1 - *s2);
++s1, ++s2;
if (s1 == e1 && s2 == e2)
return (0);
else if (s1 == e1)
return (*s2);
else if (s2 == e2)
return (*s1);
}
}
/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
* '|' delimited (possibly empty) strings in which case search for a match
* within the alternatives proceeds left to right. Return 0 for success,
* non-zero otherwise.
*/
static int altcmp(const char *s, const char *e, const char *altstr)
{
const char *p, *q;
for (q = p = altstr; ; ) {
while (*p && *p != '|')
++p;
if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
return (0);
if (!*p)
return (1);
else
q = ++p;
}
}
/* search featureset for flag *[s..e), if found set corresponding bit in
* *pval and return true, otherwise return false
*/
static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
const char **featureset)
{
uint32_t mask;
const char **ppc;
bool found = false;
for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
if (*ppc && !altcmp(s, e, *ppc)) {
*pval |= mask;
found = true;
}
}
return found;
}
static void add_flagname_to_bitmaps(const char *flagname,
FeatureWordArray words,
Error **errp)
{
FeatureWord w;
for (w = 0; w < FEATURE_WORDS; w++) {
FeatureWordInfo *wi = &feature_word_info[w];
target-i386: Move feature name arrays inside FeatureWordInfo It makes it easier to guarantee the arrays are the right size, and to find information when looking at the code. Backports commit 2d5312da566e4424a807d078da05f92ee7be3eec from qemu
2018-02-26 10:26:44 +01:00
if (lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
import
2015-08-21 09:04:50 +02:00
break;
}
}
if (w == FEATURE_WORDS) {
error_setg(errp, "CPU feature %s not found", flagname);
}
}
/* CPU class name definitions: */
#define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
#define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
/* Return type name for a given CPU model name
* Caller is responsible for freeing the returned string.
*/
static char *x86_cpu_type_name(const char *model_name)
{
return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
}
static ObjectClass *x86_cpu_class_by_name(struct uc_struct *uc, const char *cpu_model)
{
ObjectClass *oc;
char *typename;
if (cpu_model == NULL) {
return NULL;
}
typename = x86_cpu_type_name(cpu_model);
oc = object_class_by_name(uc, typename);
revert to use of g_free to make future qemu integrations easier (#695) * revert to use of g_free to make future qemu integrations easier * bracing
2016-12-21 15:28:36 +01:00
g_free(typename);
import
2015-08-21 09:04:50 +02:00
return oc;
}
struct X86CPUDefinition {
const char *name;
uint32_t level;
uint32_t xlevel;
/* vendor is zero-terminated, 12 character ASCII string */
char vendor[CPUID_VENDOR_SZ + 1];
int family;
int model;
int stepping;
FeatureWordArray features;
char model_id[48];
bool cache_info_passthrough;
};
static X86CPUDefinition builtin_x86_defs[] = {
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"qemu64",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x8000000A,
This code should now build the x86_x64-softmmu part 2.
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CPUID_VENDOR_AMD,
6, 6, 3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_1_ECX
target-i386: Remove POPCNT from qemu64 and qemu32 CPU models POPCNT is not available on Penryn and older and on Opteron_G2 and older, and we want to make the default CPU runnable in most hosts, so it won't be enabled by default in KVM mode. We should eventually have all features supported by TCG enabled by default in TCG mode, but as we don't have a good mechanism today to ensure we have different defaults in KVM and TCG mode, disable POPCNT in the qemu64 and qemu32 CPU models entirely. Backports commit 6aa91e4a0237ddcebb85e3a95e166f3b3cfa42ae from qemu
2018-02-17 21:33:25 +01:00
CPUID_EXT_SSE3 | CPUID_EXT_CX16,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_8000_0001_ECX
target-i386: Remove ABM from qemu64 CPU model ABM is not available on Sandy Bridge and older, and we want to make the default CPU runnable in most hosts, so it won't be enabled by default in KVM mode. We should eventually have all features supported by TCG enabled by default in TCG mode, but as we don't have a good mechanism today to ensure we have different defaults in KVM and TCG mode, disable ABM in the qemu64 CPU model entirely. Backports commit 711956722c6764336f8b78a2106e57c55f02f36d from qemu
2018-02-17 21:32:39 +01:00
CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
target-i386: Set constant model_id for qemu64/qemu32/athlon Newer PC machines don't set hw_version, and older machines set model-id on compat_props explicitly, so we don't need the x86_cpudef_setup() code that sets model_id using qemu_hw_version() anymore. Backports commit 9cf2cc3d8237732946720d78bf9aec0064026ed8 from qemu
2018-02-24 09:18:08 +01:00
"QEMU Virtual CPU version " QEMU_HW_VERSION
import
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},
{
This code should now build the x86_x64-softmmu part 2.
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"phenom",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
5, 0x8000001A,
This code should now build the x86_x64-softmmu part 2.
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CPUID_VENDOR_AMD,
16, 2, 3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
/* Missing: CPUID_HT */
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36 | CPUID_VME,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
CPUID_EXT_POPCNT,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
/* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
CPUID_EXT3_CR8LEG,
CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_8000_0007_EDX
0,
// FEAT_C000_0001_EDX
0,
// FEAT_KVM
0,
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
0,
// FEAT_HYPERV_EBX
0,
// FEAT_HYPERV_EDX
0,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
/* Missing: CPUID_SVM_LBRV */
// FEAT_SVM
import
2015-08-21 09:04:50 +02:00
CPUID_SVM_NPT,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
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"AMD Phenom(tm) 9550 Quad-Core Processor",
import
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},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"core2duo",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
10, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 15, 11,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
import
2015-08-21 09:04:50 +02:00
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS,
/* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST,
* CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
CPUID_EXT_CX16,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_LAHF_LM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
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"Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
import
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},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"kvm64",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
15, 6, 1,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
/* Missing: CPUID_HT */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
PPRO_FEATURES | CPUID_VME |
import
2015-08-21 09:04:50 +02:00
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36,
/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_SSE3 | CPUID_EXT_CX16,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
import
2015-08-21 09:04:50 +02:00
/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
/* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
0,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Common KVM processor",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"qemu32",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
4, 0x80000004,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 6, 3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PPRO_FEATURES,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
target-i386: Enable clflushopt/clwb/pcommit instructions These instructions are used by NVDIMM drivers and the specification is located at: https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf There instructions are available on Skylake Server. Backports commit f7fda280948a5e74aeb076ef346b991ecb173c56 from qemu
2018-02-17 21:34:45 +01:00
CPUID_EXT_SSSE3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
target-i386: Set constant model_id for qemu64/qemu32/athlon Newer PC machines don't set hw_version, and older machines set model-id on compat_props explicitly, so we don't need the x86_cpudef_setup() code that sets model_id using qemu_hw_version() anymore. Backports commit 9cf2cc3d8237732946720d78bf9aec0064026ed8 from qemu
2018-02-24 09:18:08 +01:00
"QEMU Virtual CPU version " QEMU_HW_VERSION
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"kvm32",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
5, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
15, 6, 1,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
PPRO_FEATURES | CPUID_VME |
import
2015-08-21 09:04:50 +02:00
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_SSE3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
0,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Common 32-bit KVM processor",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"coreduo",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
10, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 14, 8,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
import
2015-08-21 09:04:50 +02:00
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PPRO_FEATURES | CPUID_VME |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI |
CPUID_SS,
/* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR,
* CPUID_EXT_PDCM, CPUID_EXT_VMX */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_NX,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Genuine Intel(R) CPU T2600 @ 2.16GHz",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"486",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
1, 0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
4, 8, 0,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
I486_FEATURES,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"pentium",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
1, 0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
5, 4, 3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PENTIUM_FEATURES,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"pentium2",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
2, 0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 5, 2,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PENTIUM2_FEATURES,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"pentium3",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
3, 0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 7, 3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PENTIUM3_FEATURES,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"athlon",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
2, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_AMD,
6, 2, 3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
CPUID_MCA,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_1_ECX
0,
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
target-i386: Set constant model_id for qemu64/qemu32/athlon Newer PC machines don't set hw_version, and older machines set model-id on compat_props explicitly, so we don't need the x86_cpudef_setup() code that sets model_id using qemu_hw_version() anymore. Backports commit 9cf2cc3d8237732946720d78bf9aec0064026ed8 from qemu
2018-02-24 09:18:08 +01:00
"QEMU Virtual CPU version " QEMU_HW_VERSION
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"n270",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
10, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 28, 2,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
import
2015-08-21 09:04:50 +02:00
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
import
2015-08-21 09:04:50 +02:00
PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME |
CPUID_ACPI | CPUID_SS,
/* Some CPUs got no CPUID_SEP */
/* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2,
* CPUID_EXT_XTPR */
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
CPUID_EXT_MOVBE,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_NX,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_LAHF_LM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Conroe",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
10, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 15, 3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_LAHF_LM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Penryn",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
10, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 23, 3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_SSE3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_LAHF_LM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Nehalem",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
11, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 26, 3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_LAHF_LM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Intel Core i7 9xx (Nehalem Class Core i7)",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Westmere",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
11, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 44, 1,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_LAHF_LM,
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
// FEAT_8000_0007_EDX
0,
// FEAT_C000_0001_EDX
0,
// FEAT_KVM
0,
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
0,
// FEAT_HYPERV_EBX
0,
// FEAT_HYPERV_EDX
0,
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
// FEAT_SVM
0,
// FEAT_XSAVE
0,
// FEAT_ARAT
CPUID_6_EAX_ARAT,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Westmere E56xx/L56xx/X56xx (Nehalem-C)",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"SandyBridge",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 42, 1,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_LAHF_LM,
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1] These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-14 21:46:12 +01:00
// FEAT_8000_0007_EDX
0,
// FEAT_C000_0001_EDX
0,
// FEAT_KVM
0,
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
0,
// FEAT_HYPERV_EBX
0,
// FEAT_HYPERV_EDX
0,
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1] These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-14 21:46:12 +01:00
// FEAT_SVM
0,
// FEAT_XSAVE
CPUID_XSAVE_XSAVEOPT,
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
// FEAT_ARAT
CPUID_6_EAX_ARAT,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Intel Xeon E312xx (Sandy Bridge)",
import
2015-08-21 09:04:50 +02:00
},
target-i386: add Ivy Bridge CPU model Backports commit 2f9ac42acf4602453d5839221df6cc7cabc3355e from qemu
2018-02-14 22:20:41 +01:00
{
"IvyBridge",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x80000008,
target-i386: add Ivy Bridge CPU model Backports commit 2f9ac42acf4602453d5839221df6cc7cabc3355e from qemu
2018-02-14 22:20:41 +01:00
CPUID_VENDOR_INTEL,
6, 58, 9,
{
// FEAT_1_EDX
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
// FEAT_1_ECX
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
// FEAT_7_0_EBX
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_ERMS,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
target-i386: add Ivy Bridge CPU model Backports commit 2f9ac42acf4602453d5839221df6cc7cabc3355e from qemu
2018-02-14 22:20:41 +01:00
// FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM,
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
// FEAT_8000_0007_EDX
0,
target-i386: add Ivy Bridge CPU model Backports commit 2f9ac42acf4602453d5839221df6cc7cabc3355e from qemu
2018-02-14 22:20:41 +01:00
// FEAT_C000_0001_EDX
0,
// FEAT_KVM
0,
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
0,
// FEAT_HYPERV_EBX
0,
// FEAT_HYPERV_EDX
0,
target-i386: add Ivy Bridge CPU model Backports commit 2f9ac42acf4602453d5839221df6cc7cabc3355e from qemu
2018-02-14 22:20:41 +01:00
// FEAT_SVM
0,
// FEAT_XSAVE
CPUID_XSAVE_XSAVEOPT,
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
// FEAT_ARAT
CPUID_6_EAX_ARAT,
target-i386: add Ivy Bridge CPU model Backports commit 2f9ac42acf4602453d5839221df6cc7cabc3355e from qemu
2018-02-14 22:20:41 +01:00
},
"Intel Xeon E3-12xx v2 (Ivy Bridge)",
},
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
{
"Haswell-noTSX",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x80000008,
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
CPUID_VENDOR_INTEL,
6, 60, 1,
{
// FEAT_1_EDX
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
// FEAT_1_ECX
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
// FEAT_7_0_EBX
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
// FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX
target-i386: add ABM to Haswell* and Broadwell* CPU models ABM is only implemented as a single instruction set by AMD; all AMD processors support both instructions or neither. Intel considers POPCNT as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's ABM flag to indicate support for both POPCNT and LZCNT. It has to be added to Haswell and Broadwell because Haswell, by adding LZCNT, has completed the ABM. Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older machine types) on an Haswell-EP machine. Backports commit becb66673ec30cb604926d247ab9449a60ad8b11 from qemu
2018-02-16 06:30:47 +01:00
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
// FEAT_8000_0007_EDX
0,
// FEAT_C000_0001_EDX
0,
// FEAT_KVM
0,
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
0,
// FEAT_HYPERV_EBX
0,
// FEAT_HYPERV_EDX
0,
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
// FEAT_SVM
0,
// FEAT_XSAVE
CPUID_XSAVE_XSAVEOPT,
// FEAT_ARAT
CPUID_6_EAX_ARAT,
},
"Intel Core Processor (Haswell, no TSX)",
},
import
2015-08-21 09:04:50 +02:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Haswell",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 60, 1,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
target-i386: add f16c and rdrand to Haswell and Broadwell Both were added in Ivy Bridge (for which we do not have a CPU model yet!). Backports commit 78a611f1936b3eac8ed78a2be2146a742a85212c from qemu
2018-02-14 22:16:38 +01:00
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// FEAT_7_0_EBX
import
2015-08-21 09:04:50 +02:00
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX
target-i386: add ABM to Haswell* and Broadwell* CPU models ABM is only implemented as a single instruction set by AMD; all AMD processors support both instructions or neither. Intel considers POPCNT as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's ABM flag to indicate support for both POPCNT and LZCNT. It has to be added to Haswell and Broadwell because Haswell, by adding LZCNT, has completed the ABM. Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older machine types) on an Haswell-EP machine. Backports commit becb66673ec30cb604926d247ab9449a60ad8b11 from qemu
2018-02-16 06:30:47 +01:00
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM,
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1] These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-14 21:46:12 +01:00
// FEAT_8000_0007_EDX
0,
// FEAT_C000_0001_EDX
0,
// FEAT_KVM
0,
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
0,
// FEAT_HYPERV_EBX
0,
// FEAT_HYPERV_EDX
0,
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1] These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-14 21:46:12 +01:00
// FEAT_SVM
0,
// FEAT_XSAVE
CPUID_XSAVE_XSAVEOPT,
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
// FEAT_ARAT
CPUID_6_EAX_ARAT,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Intel Core Processor (Haswell)",
import
2015-08-21 09:04:50 +02:00
},
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
{
"Broadwell-noTSX",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x80000008,
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
CPUID_VENDOR_INTEL,
6, 61, 2,
{
// FEAT_1_EDX
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
// FEAT_1_ECX
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
// FEAT_7_0_EBX
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
// FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX
target-i386: add ABM to Haswell* and Broadwell* CPU models ABM is only implemented as a single instruction set by AMD; all AMD processors support both instructions or neither. Intel considers POPCNT as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's ABM flag to indicate support for both POPCNT and LZCNT. It has to be added to Haswell and Broadwell because Haswell, by adding LZCNT, has completed the ABM. Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older machine types) on an Haswell-EP machine. Backports commit becb66673ec30cb604926d247ab9449a60ad8b11 from qemu
2018-02-16 06:30:47 +01:00
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
// FEAT_8000_0007_EDX
0,
// FEAT_C000_0001_EDX
0,
// FEAT_KVM
0,
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
0,
// FEAT_HYPERV_EBX
0,
// FEAT_HYPERV_EDX
0,
target-i386: Haswell-noTSX and Broadwell-noTSX With the Intel microcode update that removed HLE and RTM, there will be different kinds of Haswell and Broadwell CPUs out there: some that still have the HLE and RTM features, and some that don't have the HLE and RTM features. On both cases people may be willing to use the pc-*-2.3 machine-types. So, to cover both cases, introduce Haswell-noTSX and Broadwell-noTSX CPU models, for hosts that have Haswell and Broadwell CPUs without TSX support. Backports commit a356850b80b3d13b2ef737dad2acb05e6da03753 from qemu
2018-02-14 22:39:34 +01:00
// FEAT_SVM
0,
// FEAT_XSAVE
CPUID_XSAVE_XSAVEOPT,
// FEAT_ARAT
CPUID_6_EAX_ARAT,
},
"Intel Core Processor (Broadwell, no TSX)",
},
import
2015-08-21 09:04:50 +02:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Broadwell",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_INTEL,
6, 61, 2,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
target-i386: add f16c and rdrand to Haswell and Broadwell Both were added in Ivy Bridge (for which we do not have a CPU model yet!). Backports commit 78a611f1936b3eac8ed78a2be2146a742a85212c from qemu
2018-02-14 22:16:38 +01:00
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_7_0_EBX
import
2015-08-21 09:04:50 +02:00
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX
target-i386: add ABM to Haswell* and Broadwell* CPU models ABM is only implemented as a single instruction set by AMD; all AMD processors support both instructions or neither. Intel considers POPCNT as part of SSE4.2, and LZCNT as part of BMI1, but Intel also uses AMD's ABM flag to indicate support for both POPCNT and LZCNT. It has to be added to Haswell and Broadwell because Haswell, by adding LZCNT, has completed the ABM. Tested with "qemu-kvm -cpu Haswell-noTSX,enforce" (and also with older machine types) on an Haswell-EP machine. Backports commit becb66673ec30cb604926d247ab9449a60ad8b11 from qemu
2018-02-16 06:30:47 +01:00
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1] These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-14 21:46:12 +01:00
// FEAT_8000_0007_EDX
0,
// FEAT_C000_0001_EDX
0,
// FEAT_KVM
0,
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
0,
// FEAT_HYPERV_EBX
0,
// FEAT_HYPERV_EDX
0,
target-i386: add feature flags for CPUID[EAX=0xd,ECX=1] These represent xsave-related capabilities of the processor, and KVM may or may not support them. Add feature bits so that they are considered by "-cpu ...,enforce", and use the new feature work instead of calling kvm_arch_get_supported_cpuid. Bit 3 (XSAVES) is not migratables because it requires saving MSR_IA32_XSS. Neither KVM nor any commonly available hardware supports it anyway. Backports commit 0bb0b2d2fe7f645ddaf1f0ff40ac669c9feb4aa1 from qemu also backports 18cd2c17b5370369a886155c001da0a7f54bbcca
2018-02-14 21:46:12 +01:00
// FEAT_SVM
0,
// FEAT_XSAVE
CPUID_XSAVE_XSAVEOPT,
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
// FEAT_ARAT
CPUID_6_EAX_ARAT,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Intel Core Processor (Broadwell)",
import
2015-08-21 09:04:50 +02:00
},
target-i386: add Skylake-Client cpu model Introduce Skylake-Client cpu mode which inherits the features from Broadwell and supports some additional features that are: MPX, XSAVEC, and XGETBV1. Backports commit f6f949e9295889fb272698aea763dcea77d616ce from qemu
2018-02-25 00:25:41 +01:00
{
"Skylake-Client",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x80000008,
target-i386: add Skylake-Client cpu model Introduce Skylake-Client cpu mode which inherits the features from Broadwell and supports some additional features that are: MPX, XSAVEC, and XGETBV1. Backports commit f6f949e9295889fb272698aea763dcea77d616ce from qemu
2018-02-25 00:25:41 +01:00
CPUID_VENDOR_INTEL,
6, 94, 3,
{
// FEAT_1_EDX
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
// FEAT_1_ECX
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
// FEAT_7_0_EBX
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
// FEAT_7_0_ECX
0,
// FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX
CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
// FEAT_8000_0007_EDX
0,
// FEAT_C000_0001_EDX
0,
// FEAT_KVM
0,
target-i386: Report hyperv feature words through qom This change adds hyperv feature words report through qom rpc. When VM is configured with hyperv features enabled libvirt will check that required feature words are set in cpuid leaf 40000003 through qom request. Currently qemu does not report hyperv feature words which prevents windows guests from starting with libvirt. To avoid conflicting with current hyperv properties all added feature words cannot be set directly with -cpu +feature yet. Backports commit c35bd19a5c9140bce8b913cc5cefe6f071135bdb from qemu
2018-02-25 08:45:06 +01:00
// FEAT_HYPERV_EAX
0,
// FEAT_HYPERV_EBX
0,
// FEAT_HYPERV_EDX
0,
target-i386: add Skylake-Client cpu model Introduce Skylake-Client cpu mode which inherits the features from Broadwell and supports some additional features that are: MPX, XSAVEC, and XGETBV1. Backports commit f6f949e9295889fb272698aea763dcea77d616ce from qemu
2018-02-25 00:25:41 +01:00
// FEAT_SVM
0,
/* Missing: XSAVES (not supported by some Linux versions,
* including v4.1 to v4.6).
* KVM doesn't yet expose any XSAVES state save component,
* and the only one defined in Skylake (processor tracing)
* probably will block migration anyway.
*/
// FEAT_XSAVE]
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
CPUID_XSAVE_XGETBV1,
// FEAT_6_EAX
CPUID_6_EAX_ARAT,
},
"Intel Core Processor (Skylake)",
},
import
2015-08-21 09:04:50 +02:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Opteron_G1",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
5, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_AMD,
15, 6, 1,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_SSE3,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_7_0_EBX
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"AMD Opteron 240 (Gen 1 Class Opteron)",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Opteron_G2",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
5, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_AMD,
15, 6, 1,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_CX16 | CPUID_EXT_SSE3,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_7_0_EBX
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
CPUID_EXT2_DE | CPUID_EXT2_FPU,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"AMD Opteron 22xx (Gen 2 Class Opteron)",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Opteron_G3",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
5, 0x80000008,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_AMD,
15, 6, 1,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
CPUID_EXT_SSE3,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_7_0_EBX
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
CPUID_EXT2_DE | CPUID_EXT2_FPU,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"AMD Opteron 23xx (Gen 3 Class Opteron)",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Opteron_G4",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x8000001A,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_AMD,
21, 1, 2,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_7_0_EBX
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
CPUID_EXT3_LAHF_LM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"AMD Opteron 62xx class CPU",
import
2015-08-21 09:04:50 +02:00
},
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"Opteron_G5",
target-i386: Remove unused X86CPUDefinition::xlevel2 field No CPU model in builtin_x86_defs has xlevel2 set, so it is always zero. Delete the field. Note that this is not an user-visible change. It doesn't remove the ability to set xlevel2 on the command-line, it just removes an unused field in builtin_x86_defs. Backports commit 0456441b5eb6694a561ad5bb8dad52483e6a08d0 from qemu
2018-02-26 09:55:53 +01:00
0xd, 0x8000001A,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
CPUID_VENDOR_AMD,
21, 2, 0,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_EDX
target-i386: add VME to all CPUs vm86 mode extensions date back to the 486. All models should have them. Backports commit b3a4f0b1a072a467d003755ca0e55c5be38387cb from qemu
2018-02-14 22:15:18 +01:00
CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
import
2015-08-21 09:04:50 +02:00
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
CPUID_DE | CPUID_FP87,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_1_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_7_0_EBX
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
0,
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
// FEAT_7_0_ECX
0,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_EDX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
// FEAT_8000_0001_ECX
import
2015-08-21 09:04:50 +02:00
CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
CPUID_EXT3_LAHF_LM,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
},
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
"AMD Opteron 63xx class CPU",
import
2015-08-21 09:04:50 +02:00
},
};
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
static uint32_t x86_cpu_get_supported_feature_word(struct uc_struct *uc,
FeatureWord w, bool migratable);
import
2015-08-21 09:04:50 +02:00
static void report_unavailable_features(FeatureWord w, uint32_t mask)
{
FeatureWordInfo *f = &feature_word_info[w];
int i;
for (i = 0; i < 32; ++i) {
target-i386: Use 1UL for bit shift Fix undefined behavior detected by clang runtime check: qemu/target-i386/cpu.c:1494:15: runtime error: left shift of 1 by 31 places cannot be represented in type 'int' While doing that, add extra parenthesis for clarity. Backports commit 72370dc1149d7c90d2c2218e0d0658bee23a5bf7 from qemu
2018-02-16 22:34:39 +01:00
if ((1UL << i) & mask) {
import
2015-08-21 09:04:50 +02:00
const char *reg = get_register_name_32(f->cpuid_reg);
assert(reg);
fprintf(stderr, "warning: %s doesn't support requested feature: "
"CPUID.%02XH:%s%s%s [bit %d]\n",
"TCG",
f->cpuid_eax, reg,
f->feat_names[i] ? "." : "",
f->feat_names[i] ? f->feat_names[i] : "", i);
}
}
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static void x86_cpuid_version_get_family(struct uc_struct *uc,
Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
import
2015-08-21 09:04:50 +02:00
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
int64_t value;
value = (env->cpuid_version >> 8) & 0xf;
if (value == 0xf) {
value += (env->cpuid_version >> 20) & 0xff;
}
qapi: Swap visit_* arguments for consistent 'name' placement JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Backports commit 51e72bc1dd6ace6e91d675f41a1f09bd00ab8043 from qemu
2018-02-20 04:31:04 +01:00
visit_type_int(v, name, &value, errp);
import
2015-08-21 09:04:50 +02:00
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static void x86_cpuid_version_set_family(struct uc_struct *uc,
Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
import
2015-08-21 09:04:50 +02:00
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
const int64_t min = 0;
const int64_t max = 0xff + 0xf;
Error *local_err = NULL;
int64_t value;
qapi: Swap visit_* arguments for consistent 'name' placement JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Backports commit 51e72bc1dd6ace6e91d675f41a1f09bd00ab8043 from qemu
2018-02-20 04:31:04 +01:00
visit_type_int(v, name, &value, &local_err);
import
2015-08-21 09:04:50 +02:00
if (local_err) {
error_propagate(errp, local_err);
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
return;
import
2015-08-21 09:04:50 +02:00
}
if (value < min || value > max) {
qerror: Clean up QERR_ macros to expand into a single string These macros expand into error class enumeration constant, comma, string. Unclean. Has been that way since commit 13f59ae. The error class is always ERROR_CLASS_GENERIC_ERROR since the previous commit. * Prepend every use of a QERR_ macro by ERROR_CLASS_GENERIC_ERROR, and delete it from the QERR_ macro. No change after preprocessing. * Rewrite error_set(ERROR_CLASS_GENERIC_ERROR, ...) into error_setg(...). Again, no change after preprocessing. Backports commit c6bd8c706a799eb0fece99f468aaa22b818036f3 from qemu
2018-02-13 23:34:32 +01:00
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
name ? name : "null", value, min, max);
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
return;
import
2015-08-21 09:04:50 +02:00
}
env->cpuid_version &= ~0xff00f00;
if (value > 0x0f) {
env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
} else {
env->cpuid_version |= value << 8;
}
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static void x86_cpuid_version_get_model(struct uc_struct *uc,
Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
import
2015-08-21 09:04:50 +02:00
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
int64_t value;
value = (env->cpuid_version >> 4) & 0xf;
value |= ((env->cpuid_version >> 16) & 0xf) << 4;
qapi: Swap visit_* arguments for consistent 'name' placement JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Backports commit 51e72bc1dd6ace6e91d675f41a1f09bd00ab8043 from qemu
2018-02-20 04:31:04 +01:00
visit_type_int(v, name, &value, errp);
import
2015-08-21 09:04:50 +02:00
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static void x86_cpuid_version_set_model(struct uc_struct *uc,
Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
import
2015-08-21 09:04:50 +02:00
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
const int64_t min = 0;
const int64_t max = 0xff;
Error *local_err = NULL;
int64_t value;
qapi: Swap visit_* arguments for consistent 'name' placement JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Backports commit 51e72bc1dd6ace6e91d675f41a1f09bd00ab8043 from qemu
2018-02-20 04:31:04 +01:00
visit_type_int(v, name, &value, &local_err);
import
2015-08-21 09:04:50 +02:00
if (local_err) {
error_propagate(errp, local_err);
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
return;
import
2015-08-21 09:04:50 +02:00
}
if (value < min || value > max) {
qerror: Clean up QERR_ macros to expand into a single string These macros expand into error class enumeration constant, comma, string. Unclean. Has been that way since commit 13f59ae. The error class is always ERROR_CLASS_GENERIC_ERROR since the previous commit. * Prepend every use of a QERR_ macro by ERROR_CLASS_GENERIC_ERROR, and delete it from the QERR_ macro. No change after preprocessing. * Rewrite error_set(ERROR_CLASS_GENERIC_ERROR, ...) into error_setg(...). Again, no change after preprocessing. Backports commit c6bd8c706a799eb0fece99f468aaa22b818036f3 from qemu
2018-02-13 23:34:32 +01:00
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
name ? name : "null", value, min, max);
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
return;
import
2015-08-21 09:04:50 +02:00
}
env->cpuid_version &= ~0xf00f0;
env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static void x86_cpuid_version_get_stepping(struct uc_struct *uc,
Object *obj, Visitor *v,
const char *name, void *opaque,
import
2015-08-21 09:04:50 +02:00
Error **errp)
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
int64_t value;
value = env->cpuid_version & 0xf;
qapi: Swap visit_* arguments for consistent 'name' placement JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Backports commit 51e72bc1dd6ace6e91d675f41a1f09bd00ab8043 from qemu
2018-02-20 04:31:04 +01:00
visit_type_int(v, name, &value, errp);
import
2015-08-21 09:04:50 +02:00
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static void x86_cpuid_version_set_stepping(struct uc_struct *uc,
Object *obj, Visitor *v,
const char *name, void *opaque,
import
2015-08-21 09:04:50 +02:00
Error **errp)
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
const int64_t min = 0;
const int64_t max = 0xf;
Error *local_err = NULL;
int64_t value;
qapi: Swap visit_* arguments for consistent 'name' placement JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Backports commit 51e72bc1dd6ace6e91d675f41a1f09bd00ab8043 from qemu
2018-02-20 04:31:04 +01:00
visit_type_int(v, name, &value, &local_err);
import
2015-08-21 09:04:50 +02:00
if (local_err) {
error_propagate(errp, local_err);
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
return;
import
2015-08-21 09:04:50 +02:00
}
if (value < min || value > max) {
qerror: Clean up QERR_ macros to expand into a single string These macros expand into error class enumeration constant, comma, string. Unclean. Has been that way since commit 13f59ae. The error class is always ERROR_CLASS_GENERIC_ERROR since the previous commit. * Prepend every use of a QERR_ macro by ERROR_CLASS_GENERIC_ERROR, and delete it from the QERR_ macro. No change after preprocessing. * Rewrite error_set(ERROR_CLASS_GENERIC_ERROR, ...) into error_setg(...). Again, no change after preprocessing. Backports commit c6bd8c706a799eb0fece99f468aaa22b818036f3 from qemu
2018-02-13 23:34:32 +01:00
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
name ? name : "null", value, min, max);
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
return;
import
2015-08-21 09:04:50 +02:00
}
env->cpuid_version &= ~0xf;
env->cpuid_version |= value & 0xf;
}
static char *x86_cpuid_get_vendor(struct uc_struct *uc, Object *obj, Error **errp)
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
char *value;
value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
env->cpuid_vendor3);
return value;
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static int x86_cpuid_set_vendor(struct uc_struct *uc, Object *obj,
const char *value, Error **errp)
import
2015-08-21 09:04:50 +02:00
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
int i;
if (strlen(value) != CPUID_VENDOR_SZ) {
qerror: Clean up QERR_ macros to expand into a single string These macros expand into error class enumeration constant, comma, string. Unclean. Has been that way since commit 13f59ae. The error class is always ERROR_CLASS_GENERIC_ERROR since the previous commit. * Prepend every use of a QERR_ macro by ERROR_CLASS_GENERIC_ERROR, and delete it from the QERR_ macro. No change after preprocessing. * Rewrite error_set(ERROR_CLASS_GENERIC_ERROR, ...) into error_setg(...). Again, no change after preprocessing. Backports commit c6bd8c706a799eb0fece99f468aaa22b818036f3 from qemu
2018-02-13 23:34:32 +01:00
error_setg(errp, QERR_PROPERTY_VALUE_BAD, "",
"vendor", value);
handle some errors properly so avoid exit() during initialization. this fixes issue #237
2015-11-11 18:43:41 +01:00
return -1;
import
2015-08-21 09:04:50 +02:00
}
env->cpuid_vendor1 = 0;
env->cpuid_vendor2 = 0;
env->cpuid_vendor3 = 0;
for (i = 0; i < 4; i++) {
env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
}
handle some errors properly so avoid exit() during initialization. this fixes issue #237
2015-11-11 18:43:41 +01:00
return 0;
import
2015-08-21 09:04:50 +02:00
}
static char *x86_cpuid_get_model_id(struct uc_struct *uc, Object *obj, Error **errp)
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
char *value;
int i;
value = g_malloc(48 + 1);
for (i = 0; i < 48; i++) {
value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
}
value[48] = '\0';
return value;
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static int x86_cpuid_set_model_id(struct uc_struct *uc, Object *obj,
const char *model_id, Error **errp)
import
2015-08-21 09:04:50 +02:00
{
X86CPU *cpu = X86_CPU(uc, obj);
CPUX86State *env = &cpu->env;
int c, len, i;
if (model_id == NULL) {
model_id = "";
}
len = strlen(model_id);
memset(env->cpuid_model, 0, 48);
for (i = 0; i < 48; i++) {
if (i >= len) {
c = '\0';
} else {
c = (uint8_t)model_id[i];
}
env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
}
handle some errors properly so avoid exit() during initialization. this fixes issue #237
2015-11-11 18:43:41 +01:00
return 0;
import
2015-08-21 09:04:50 +02:00
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static void x86_cpuid_get_tsc_freq(struct uc_struct *uc,
Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
import
2015-08-21 09:04:50 +02:00
{
X86CPU *cpu = X86_CPU(uc, obj);
int64_t value;
value = cpu->env.tsc_khz * 1000;
qapi: Swap visit_* arguments for consistent 'name' placement JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Backports commit 51e72bc1dd6ace6e91d675f41a1f09bd00ab8043 from qemu
2018-02-20 04:31:04 +01:00
visit_type_int(v, name, &value, errp);
import
2015-08-21 09:04:50 +02:00
}
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static void x86_cpuid_set_tsc_freq(struct uc_struct *uc,
Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
import
2015-08-21 09:04:50 +02:00
{
X86CPU *cpu = X86_CPU(uc, obj);
const int64_t min = 0;
const int64_t max = INT64_MAX;
Error *local_err = NULL;
int64_t value;
qapi: Swap visit_* arguments for consistent 'name' placement JSON uses "name":value, but many of our visitor interfaces were called with visit_type_FOO(v, &value, name, errp). This can be a bit confusing to have to mentally swap the parameter order to match JSON order. It's particularly bad for visit_start_struct(), where the 'name' parameter is smack in the middle of the otherwise-related group of 'obj, kind, size' parameters! It's time to do a global swap of the parameter ordering, so that the 'name' parameter is always immediately after the Visitor argument. Additional reason in favor of the swap: the existing include/qjson.h prefers listing 'name' first in json_prop_*(), and I have plans to unify that file with the qapi visitors; listing 'name' first in qapi will minimize churn to the (admittedly few) qjson.h clients. Later patches will then fix docs, object.h, visitor-impl.h, and those clients to match. Done by first patching scripts/qapi*.py by hand to make generated files do what I want, then by running the following Coccinelle script to affect the rest of the code base: $ spatch --sp-file script `git grep -l '\bvisit_' -- '**/*.[ch]'` I then had to apply some touchups (Coccinelle insisted on TAB indentation in visitor.h, and botched the signature of visit_type_enum() by rewriting 'const char *const strings[]' to the syntactically invalid 'const char*const[] strings'). The movement of parameters is sufficient to provoke compiler errors if any callers were missed. // Part 1: Swap declaration order @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_start_struct -(TV v, TObj OBJ, T1 ARG1, const char *name, T2 ARG2, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type bool, TV, T1; identifier ARG1; @@ bool visit_optional -(TV v, T1 ARG1, const char *name) +(TV v, const char *name, T1 ARG1) { ... } @@ type TV, TErr, TObj, T1; identifier OBJ, ARG1; @@ void visit_get_next_type -(TV v, TObj OBJ, T1 ARG1, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, TErr errp) { ... } @@ type TV, TErr, TObj, T1, T2; identifier OBJ, ARG1, ARG2; @@ void visit_type_enum -(TV v, TObj OBJ, T1 ARG1, T2 ARG2, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, T1 ARG1, T2 ARG2, TErr errp) { ... } @@ type TV, TErr, TObj; identifier OBJ; identifier VISIT_TYPE =~ "^visit_type_"; @@ void VISIT_TYPE -(TV v, TObj OBJ, const char *name, TErr errp) +(TV v, const char *name, TObj OBJ, TErr errp) { ... } // Part 2: swap caller order @@ expression V, NAME, OBJ, ARG1, ARG2, ERR; identifier VISIT_TYPE =~ "^visit_type_"; @@ ( -visit_start_struct(V, OBJ, ARG1, NAME, ARG2, ERR) +visit_start_struct(V, NAME, OBJ, ARG1, ARG2, ERR) | -visit_optional(V, ARG1, NAME) +visit_optional(V, NAME, ARG1) | -visit_get_next_type(V, OBJ, ARG1, NAME, ERR) +visit_get_next_type(V, NAME, OBJ, ARG1, ERR) | -visit_type_enum(V, OBJ, ARG1, ARG2, NAME, ERR) +visit_type_enum(V, NAME, OBJ, ARG1, ARG2, ERR) | -VISIT_TYPE(V, OBJ, NAME, ERR) +VISIT_TYPE(V, NAME, OBJ, ERR) ) Backports commit 51e72bc1dd6ace6e91d675f41a1f09bd00ab8043 from qemu
2018-02-20 04:31:04 +01:00
visit_type_int(v, name, &value, &local_err);
import
2015-08-21 09:04:50 +02:00
if (local_err) {
error_propagate(errp, local_err);
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
return;
import
2015-08-21 09:04:50 +02:00
}
if (value < min || value > max) {
qerror: Clean up QERR_ macros to expand into a single string These macros expand into error class enumeration constant, comma, string. Unclean. Has been that way since commit 13f59ae. The error class is always ERROR_CLASS_GENERIC_ERROR since the previous commit. * Prepend every use of a QERR_ macro by ERROR_CLASS_GENERIC_ERROR, and delete it from the QERR_ macro. No change after preprocessing. * Rewrite error_set(ERROR_CLASS_GENERIC_ERROR, ...) into error_setg(...). Again, no change after preprocessing. Backports commit c6bd8c706a799eb0fece99f468aaa22b818036f3 from qemu
2018-02-13 23:34:32 +01:00
error_setg(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
name ? name : "null", value, min, max);
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
return;
import
2015-08-21 09:04:50 +02:00
}
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
cpu->env.tsc_khz = (int)(value / 1000);
import
2015-08-21 09:04:50 +02:00
}
/* Generic getter for "feature-words" and "filtered-features" properties */
qom: Swap 'name' next to visitor in ObjectPropertyAccessor Similar to the previous patch, it's nice to have all functions in the tree that involve a visitor and a name for conversion to or from QAPI to consistently stick the 'name' parameter next to the Visitor parameter. Done by manually changing include/qom/object.h and qom/object.c, then running this Coccinelle script and touching up the fallout (Coccinelle insisted on adding some trailing whitespace). @ rule1 @ identifier fn; typedef Object, Visitor, Error; identifier obj, v, opaque, name, errp; @@ void fn - (Object *obj, Visitor *v, void *opaque, const char *name, + (Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ... } @@ identifier rule1.fn; expression obj, v, opaque, name, errp; @@ fn(obj, v, - opaque, name, + name, opaque, errp) Backports commit d7bce9999df85c56c8cb1fcffd944d51bff8ff48 from qemu
2018-02-20 04:57:03 +01:00
static void x86_cpu_get_feature_words(struct uc_struct *uc,
Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
import
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{
uint32_t *array = (uint32_t *)opaque;
FeatureWord w;
error: Remove unnecessary local_err variables This patch simplifies code that uses a local_err variable just to immediately use it for an error_propagate() call. Coccinelle patch used to perform the changes added to scripts/coccinelle/remove_local_err.cocci. Backports commit 6b62d961373e0327f2af8fb77d6d5d6308864180 from qemu
2018-02-25 01:12:16 +01:00
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
// These all get setup below, so no need to initialise them here.
X86CPUFeatureWordInfo word_infos[FEATURE_WORDS];
Fixed warning about {} initialisers.
2017-01-21 01:41:11 +01:00
X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS];
import
2015-08-21 09:04:50 +02:00
X86CPUFeatureWordInfoList *list = NULL;
for (w = 0; w < FEATURE_WORDS; w++) {
FeatureWordInfo *wi = &feature_word_info[w];
X86CPUFeatureWordInfo *qwi = &word_infos[w];
qwi->cpuid_input_eax = wi->cpuid_eax;
qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
qwi->cpuid_input_ecx = wi->cpuid_ecx;
qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
qwi->features = array[w];
/* List will be in reverse order, but order shouldn't matter */
list_entries[w].next = list;
list_entries[w].value = &word_infos[w];
list = &list_entries[w];
}
error: Remove unnecessary local_err variables This patch simplifies code that uses a local_err variable just to immediately use it for an error_propagate() call. Coccinelle patch used to perform the changes added to scripts/coccinelle/remove_local_err.cocci. Backports commit 6b62d961373e0327f2af8fb77d6d5d6308864180 from qemu
2018-02-25 01:12:16 +01:00
visit_type_X86CPUFeatureWordInfoList(v, "feature-words", &list, errp);
import
2015-08-21 09:04:50 +02:00
}
/* Convert all '_' in a feature string option name to '-', to make feature
* name conform to QOM property naming rule, which uses '-' instead of '_'.
*/
static inline void feat2prop(char *s)
{
while ((s = strchr(s, '_'))) {
*s = '-';
}
}
/* Parse "+feature,-feature,feature=foo" CPU feature string
*/
static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
Error **errp)
{
X86CPU *cpu = X86_CPU(cs->uc, cs);
char *featurestr; /* Single 'key=value" string being parsed */
Error *local_err = NULL;
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
// Unicorn: added for consistent zeroing out
memset(cpu->plus_features, 0, sizeof(cpu->plus_features));
memset(cpu->minus_features, 0, sizeof(cpu->minus_features));
target-i386: Consolidate calls of object_property_parse() in x86_cpu_parse_featurestr Backports commit f6750e959a397dea988efd4e488e1ff813011065 from qemu
2018-02-25 00:53:09 +01:00
if (!features) {
return;
}
for (featurestr = strtok(features, ",");
featurestr && !local_err;
featurestr = strtok(NULL, ",")) {
const char *name;
const char *val = NULL;
char *eq = NULL;
target-i386: Avoid using locals outside their scope x86_cpu_parse_featurestr has a "val = num;" assignment just before num goes out of scope. Push num up to fix the issue. Backports commit cf2887c9738451eb989c6c102af070dee2dc172a from qemu
2018-02-25 08:30:03 +01:00
char num[32];
import
2015-08-21 09:04:50 +02:00
target-i386: Consolidate calls of object_property_parse() in x86_cpu_parse_featurestr Backports commit f6750e959a397dea988efd4e488e1ff813011065 from qemu
2018-02-25 00:53:09 +01:00
/* Compatibility syntax: */
import
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if (featurestr[0] == '+') {
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
add_flagname_to_bitmaps(featurestr + 1, cpu->plus_features, &local_err);
target-i386: Consolidate calls of object_property_parse() in x86_cpu_parse_featurestr Backports commit f6750e959a397dea988efd4e488e1ff813011065 from qemu
2018-02-25 00:53:09 +01:00
continue;
import
2015-08-21 09:04:50 +02:00
} else if (featurestr[0] == '-') {
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
add_flagname_to_bitmaps(featurestr + 1, cpu->minus_features, &local_err);
target-i386: Consolidate calls of object_property_parse() in x86_cpu_parse_featurestr Backports commit f6750e959a397dea988efd4e488e1ff813011065 from qemu
2018-02-25 00:53:09 +01:00
continue;
}
eq = strchr(featurestr, '=');
if (eq) {
*eq++ = 0;
val = eq;
import
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} else {
target-i386: Consolidate calls of object_property_parse() in x86_cpu_parse_featurestr Backports commit f6750e959a397dea988efd4e488e1ff813011065 from qemu
2018-02-25 00:53:09 +01:00
val = "on";
import
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}
target-i386: Consolidate calls of object_property_parse() in x86_cpu_parse_featurestr Backports commit f6750e959a397dea988efd4e488e1ff813011065 from qemu
2018-02-25 00:53:09 +01:00
feat2prop(featurestr);
name = featurestr;
/* Special case: */
if (!strcmp(name, "tsc-freq")) {
int64_t tsc_freq;
char *err;
tsc_freq = qemu_strtosz_suffix_unit(val, &err,
QEMU_STRTOSZ_DEFSUFFIX_B, 1000);
if (tsc_freq < 0 || *err) {
error_setg(errp, "bad numerical value %s", val);
return;
}
snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
val = num;
name = "tsc-frequency";
import
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}
target-i386: Consolidate calls of object_property_parse() in x86_cpu_parse_featurestr Backports commit f6750e959a397dea988efd4e488e1ff813011065 from qemu
2018-02-25 00:53:09 +01:00
object_property_parse(cs->uc, OBJECT(cpu), val, name, &local_err);
}
if (local_err) {
error_propagate(errp, local_err);
import
2015-08-21 09:04:50 +02:00
}
}
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
static uint32_t x86_cpu_get_supported_feature_word(struct uc_struct *uc,
FeatureWord w, bool migratable_only)
import
2015-08-21 09:04:50 +02:00
{
FeatureWordInfo *wi = &feature_word_info[w];
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
uint32_t r;
import
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if (tcg_enabled(uc)) {
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
r = wi->tcg_features;
import
2015-08-21 09:04:50 +02:00
} else {
return ~0;
}
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
if (migratable_only) {
r &= x86_cpu_get_migratable_flags(w);
}
return r;
import
2015-08-21 09:04:50 +02:00
}
/*
* Filters CPU feature words based on host availability of each feature.
*
* Returns: 0 if all flags are supported by the host, non-zero otherwise.
*/
static int x86_cpu_filter_features(X86CPU *cpu)
{
CPUX86State *env = &cpu->env;
FeatureWord w;
int rv = 0;
for (w = 0; w < FEATURE_WORDS; w++) {
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
uint32_t host_feat = x86_cpu_get_supported_feature_word(env->uc, w, cpu->migratable);
import
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uint32_t requested_features = env->features[w];
env->features[w] &= host_feat;
cpu->filtered_features[w] = requested_features & ~env->features[w];
if (cpu->filtered_features[w]) {
if (cpu->check_cpuid || cpu->enforce_cpuid) {
report_unavailable_features(w, cpu->filtered_features[w]);
}
rv = 1;
}
}
return rv;
}
/* Load data from X86CPUDefinition
*/
static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
{
CPUX86State *env = &cpu->env;
const char *vendor;
FeatureWord w;
object_property_set_int(env->uc, OBJECT(cpu), def->level, "level", errp);
object_property_set_int(env->uc, OBJECT(cpu), def->family, "family", errp);
object_property_set_int(env->uc, OBJECT(cpu), def->model, "model", errp);
object_property_set_int(env->uc, OBJECT(cpu), def->stepping, "stepping", errp);
object_property_set_int(env->uc, OBJECT(cpu), def->xlevel, "xlevel", errp);
cpu->cache_info_passthrough = def->cache_info_passthrough;
object_property_set_str(env->uc, OBJECT(cpu), def->model_id, "model-id", errp);
for (w = 0; w < FEATURE_WORDS; w++) {
env->features[w] = def->features[w];
}
env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
/* sysenter isn't supported in compatibility mode on AMD,
* syscall isn't supported in compatibility mode on Intel.
* Normally we advertise the actual CPU vendor, but you can
* override this using the 'vendor' property if you want to use
* KVM's sysenter/syscall emulation in compatibility mode and
* when doing cross vendor migration
*/
vendor = def->vendor;
object_property_set_str(env->uc, OBJECT(cpu), vendor, "vendor", errp);
}
X86CPU *cpu_x86_create(struct uc_struct *uc, const char *cpu_model, Error **errp)
{
X86CPU *cpu = NULL;
ObjectClass *oc;
gchar **model_pieces;
char *name, *features;
Error *error = NULL;
model_pieces = g_strsplit(cpu_model, ",", 2);
if (!model_pieces[0]) {
error_setg(&error, "Invalid/empty CPU model name");
goto out;
}
name = model_pieces[0];
features = model_pieces[1];
oc = x86_cpu_class_by_name(uc, name);
if (oc == NULL) {
error_setg(&error, "Unable to find CPU definition: %s", name);
goto out;
}
cpu = X86_CPU(uc, object_new(uc, object_class_get_name(oc)));
x86_cpu_parse_featurestr(CPU(cpu), features, &error);
if (error) {
goto out;
}
out:
if (error != NULL) {
error_propagate(errp, error);
if (cpu) {
object_unref(uc, OBJECT(cpu));
cpu = NULL;
}
}
g_strfreev(model_pieces);
return cpu;
}
target-i386: Eliminate cpu_init() function Instead of putting extra logic inside cpu.h, just do everything inside cpu_x86_init_user(). Backports commit 15258d46baef5f8265ad5f1002905664cf58f051 from qem
2018-02-12 21:34:30 +01:00
CPUX86State *cpu_x86_init_user(struct uc_struct *uc, const char *cpu_model)
import
2015-08-21 09:04:50 +02:00
{
Error *error = NULL;
X86CPU *cpu;
cpu = cpu_x86_create(uc, cpu_model, &error);
if (error) {
target-i386: Simplify error handling on cpu_x86_init_user() Isolate error handling path from the "if (error)" checks. Backports commit 18b0e4e77142ace948497a053bd5b56c1b849592 from qemu
2018-02-12 21:37:43 +01:00
goto error;
import
2015-08-21 09:04:50 +02:00
}
target-i386: Set APIC ID using cpu_index on CONFIG_USER The PC CPU initialization code already sets apic-id based on the CPU topology, and CONFIG_USER doesn't need the topology-based APIC ID calculation code. Make CONFIG_USER set apic-id before realizing the CPU (just like PC already does), so we can simplify x86_cpu_initfn later. As there is no CPU topology configuration in CONFIG_USER, just use cpu_index as the APIC ID. Backports commit 9c235e83f1c3437be6ca45755909efb745c10deb from qemu
2018-02-12 21:46:03 +01:00
object_property_set_int(uc, OBJECT(cpu), CPU(cpu)->cpu_index, "apic-id",
&error);
if (error) {
goto error;
}
import
2015-08-21 09:04:50 +02:00
object_property_set_bool(uc, OBJECT(cpu), true, "realized", &error);
target-i386: Set APIC ID using cpu_index on CONFIG_USER The PC CPU initialization code already sets apic-id based on the CPU topology, and CONFIG_USER doesn't need the topology-based APIC ID calculation code. Make CONFIG_USER set apic-id before realizing the CPU (just like PC already does), so we can simplify x86_cpu_initfn later. As there is no CPU topology configuration in CONFIG_USER, just use cpu_index as the APIC ID. Backports commit 9c235e83f1c3437be6ca45755909efb745c10deb from qemu
2018-02-12 21:46:03 +01:00
if (error) {
goto error;
}
target-i386: Simplify error handling on cpu_x86_init_user() Isolate error handling path from the "if (error)" checks. Backports commit 18b0e4e77142ace948497a053bd5b56c1b849592 from qemu
2018-02-12 21:37:43 +01:00
return &cpu->env;
import
2015-08-21 09:04:50 +02:00
target-i386: Simplify error handling on cpu_x86_init_user() Isolate error handling path from the "if (error)" checks. Backports commit 18b0e4e77142ace948497a053bd5b56c1b849592 from qemu
2018-02-12 21:37:43 +01:00
error:
error_free(error);
if (cpu != NULL) {
object_unref(uc, OBJECT(cpu));
import
2015-08-21 09:04:50 +02:00
}
target-i386: Simplify error handling on cpu_x86_init_user() Isolate error handling path from the "if (error)" checks. Backports commit 18b0e4e77142ace948497a053bd5b56c1b849592 from qemu
2018-02-12 21:37:43 +01:00
return NULL;
import
2015-08-21 09:04:50 +02:00
}
static void x86_cpu_cpudef_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
{
X86CPUDefinition *cpudef = data;
X86CPUClass *xcc = X86_CPU_CLASS(uc, oc);
xcc->cpu_def = cpudef;
}
static void x86_register_cpudef_type(struct uc_struct *uc, X86CPUDefinition *def)
{
char *typename = x86_cpu_type_name(def->name);
TypeInfo ti = {
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
typename,
TYPE_X86_CPU,
cleanup after msvc port
2017-01-22 14:27:17 +01:00
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
0,
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
0,
NULL,
NULL,
NULL,
NULL,
cleanup after msvc port
2017-01-22 14:27:17 +01:00
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
def,
cleanup after msvc port
2017-01-22 14:27:17 +01:00
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
x86_cpu_cpudef_class_init,
import
2015-08-21 09:04:50 +02:00
};
type_register(uc, &ti);
revert to use of g_free to make future qemu integrations easier (#695) * revert to use of g_free to make future qemu integrations easier * bracing
2016-12-21 15:28:36 +01:00
g_free(typename);
import
2015-08-21 09:04:50 +02:00
}
#if !defined(CONFIG_USER_ONLY)
void cpu_clear_apic_feature(CPUX86State *env)
{
env->features[FEAT_1_EDX] &= ~CPUID_APIC;
}
#endif /* !CONFIG_USER_ONLY */
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
X86CPU *cpu = x86_env_get_cpu(env);
CPUState *cs = CPU(cpu);
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Backports commit 14c985cffa6cb177fc01a163d8bcf227c104718c from qemu
2018-02-26 05:16:03 +01:00
uint32_t pkg_offset;
import
2015-08-21 09:04:50 +02:00
/* test if maximum index reached */
if (index & 0x80000000) {
if (index > env->cpuid_xlevel) {
if (env->cpuid_xlevel2 > 0) {
/* Handle the Centaur's CPUID instruction. */
if (index > env->cpuid_xlevel2) {
index = env->cpuid_xlevel2;
} else if (index < 0xC0000000) {
index = env->cpuid_xlevel;
}
} else {
/* Intel documentation states that invalid EAX input will
* return the same information as EAX=cpuid_level
* (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
*/
index = env->cpuid_level;
}
}
} else {
if (index > env->cpuid_level)
index = env->cpuid_level;
}
switch(index) {
case 0:
*eax = env->cpuid_level;
target-i386: Eliminate unnecessary get_cpuid_vendor() function The function was used in only two places. In one of them, the function made the code less readable by requiring temporary te[bcd]x variables. In the other one we can simply inline the existing code. Backports commit 08e1a1e5a175ecbfdb761db5a62090498f736969 from qemu
2018-02-12 21:25:31 +01:00
*ebx = env->cpuid_vendor1;
*edx = env->cpuid_vendor2;
*ecx = env->cpuid_vendor3;
import
2015-08-21 09:04:50 +02:00
break;
case 1:
*eax = env->cpuid_version;
target-i386: Move CPUX86State.cpuid_apic_id to X86CPU.apic_id The field doesn't need to be inside CPUState, and it is not specific for the CPUID instruction, so move and rename it. Backports commit 9e9d3863adcbd1ffeca30f240f49805b00ba0d87 from qemu
2018-02-12 21:41:30 +01:00
*ebx = (cpu->apic_id << 24) |
8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
import
2015-08-21 09:04:50 +02:00
*ecx = env->features[FEAT_1_ECX];
target-i386: Add XSAVE extension This includes XSAVE, XRSTOR, XGETBV, XSETBV, which are all related, as well as the associate cpuid bits. Backports commit 19dc85dba23c0db1ca932c62e453c37e00761628 from qemu
2018-02-20 18:46:01 +01:00
if ((*ecx & CPUID_EXT_XSAVE) && (env->cr[4] & CR4_OSXSAVE_MASK)) {
*ecx |= CPUID_EXT_OSXSAVE;
}
import
2015-08-21 09:04:50 +02:00
*edx = env->features[FEAT_1_EDX];
if (cs->nr_cores * cs->nr_threads > 1) {
*ebx |= (cs->nr_cores * cs->nr_threads) << 16;
target-i386: Add XSAVE extension This includes XSAVE, XRSTOR, XGETBV, XSETBV, which are all related, as well as the associate cpuid bits. Backports commit 19dc85dba23c0db1ca932c62e453c37e00761628 from qemu
2018-02-20 18:46:01 +01:00
*edx |= CPUID_HT;
import
2015-08-21 09:04:50 +02:00
}
break;
case 2:
/* cache info: needed for Pentium Pro compatibility */
if (cpu->cache_info_passthrough) {
host_cpuid(index, 0, eax, ebx, ecx, edx);
break;
}
*eax = 1; /* Number of CPUID[EAX=2] calls required */
*ebx = 0;
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Backports commit 14c985cffa6cb177fc01a163d8bcf227c104718c from qemu
2018-02-26 05:16:03 +01:00
if (!cpu->enable_l3_cache) {
*ecx = 0;
} else {
*ecx = L3_N_DESCRIPTOR;
}
import
2015-08-21 09:04:50 +02:00
*edx = (L1D_DESCRIPTOR << 16) | \
(L1I_DESCRIPTOR << 8) | \
(L2_DESCRIPTOR);
break;
case 4:
/* cache info: needed for Core compatibility */
if (cpu->cache_info_passthrough) {
host_cpuid(index, count, eax, ebx, ecx, edx);
*eax &= ~0xFC000000;
} else {
*eax = 0;
switch (count) {
case 0: /* L1 dcache info */
*eax |= CPUID_4_TYPE_DCACHE | \
CPUID_4_LEVEL(1) | \
CPUID_4_SELF_INIT_LEVEL;
*ebx = (L1D_LINE_SIZE - 1) | \
((L1D_PARTITIONS - 1) << 12) | \
((L1D_ASSOCIATIVITY - 1) << 22);
*ecx = L1D_SETS - 1;
*edx = CPUID_4_NO_INVD_SHARING;
break;
case 1: /* L1 icache info */
*eax |= CPUID_4_TYPE_ICACHE | \
CPUID_4_LEVEL(1) | \
CPUID_4_SELF_INIT_LEVEL;
*ebx = (L1I_LINE_SIZE - 1) | \
((L1I_PARTITIONS - 1) << 12) | \
((L1I_ASSOCIATIVITY - 1) << 22);
*ecx = L1I_SETS - 1;
*edx = CPUID_4_NO_INVD_SHARING;
break;
case 2: /* L2 cache info */
*eax |= CPUID_4_TYPE_UNIFIED | \
CPUID_4_LEVEL(2) | \
CPUID_4_SELF_INIT_LEVEL;
if (cs->nr_threads > 1) {
*eax |= (cs->nr_threads - 1) << 14;
}
*ebx = (L2_LINE_SIZE - 1) | \
((L2_PARTITIONS - 1) << 12) | \
((L2_ASSOCIATIVITY - 1) << 22);
*ecx = L2_SETS - 1;
*edx = CPUID_4_NO_INVD_SHARING;
break;
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Backports commit 14c985cffa6cb177fc01a163d8bcf227c104718c from qemu
2018-02-26 05:16:03 +01:00
case 3: /* L3 cache info */
if (!cpu->enable_l3_cache) {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
}
*eax |= CPUID_4_TYPE_UNIFIED | \
CPUID_4_LEVEL(3) | \
CPUID_4_SELF_INIT_LEVEL;
pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
*eax |= ((1 << pkg_offset) - 1) << 14;
*ebx = (L3_N_LINE_SIZE - 1) | \
((L3_N_PARTITIONS - 1) << 12) | \
((L3_N_ASSOCIATIVITY - 1) << 22);
*ecx = L3_N_SETS - 1;
*edx = CPUID_4_INCLUSIVE | CPUID_4_COMPLEX_IDX;
break;
import
2015-08-21 09:04:50 +02:00
default: /* end of info */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
}
}
/* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
if ((*eax & 31) && cs->nr_cores > 1) {
*eax |= (cs->nr_cores - 1) << 26;
}
break;
case 5:
/* mwait info: needed for Core compatibility */
*eax = 0; /* Smallest monitor-line size in bytes */
*ebx = 0; /* Largest monitor-line size in bytes */
*ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
*edx = 0;
break;
case 6:
/* Thermal and Power Leaf */
i386: Introduce ARAT CPU feature ARAT signals that the APIC timer does not stop in power saving states. As our APICs are emulated, it's fine to expose this feature to guests, at least when asking for KVM host features or with CPU types that include the flag. The exact model number that introduced the feature is not known, but reports can be found that it's at least available since Sandy Bridge. Backports commit 28b8e4d0bf93ba176b4b7be819d537383c5a9060 from qemu
2018-02-14 22:28:05 +01:00
*eax = env->features[FEAT_6_EAX];
import
2015-08-21 09:04:50 +02:00
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 7:
/* Structured Extended Feature Flags Enumeration Leaf */
if (count == 0) {
*eax = 0; /* Maximum ECX value for sub-leaves */
*ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
target-i386: Add PKU and and OSPKE support Add PKU and OSPKE CPUID features, including xsave state and migration support. Backports commit f74eefe0b98cd7e13825de8e8d9f32e22aed102c from qemu
2018-02-19 06:06:41 +01:00
*ecx = env->features[FEAT_7_0_ECX]; /* Feature flags */
target-i386: implement PKE for TCG Backports commit 0f70ed4759a29ca932af1e9525729f4f455642f8 from qemu
2018-02-22 16:18:48 +01:00
if ((*ecx & CPUID_7_0_ECX_PKU) && env->cr[4] & CR4_PKE_MASK) {
*ecx |= CPUID_7_0_ECX_OSPKE;
}
import
2015-08-21 09:04:50 +02:00
*edx = 0; /* Reserved */
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 9:
/* Direct Cache Access Information Leaf */
*eax = 0; /* Bits 0-31 in DCA_CAP MSR */
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0xA:
/* Architectural Performance Monitoring Leaf */
target-i386: Add XSAVE extension This includes XSAVE, XRSTOR, XGETBV, XSETBV, which are all related, as well as the associate cpuid bits. Backports commit 19dc85dba23c0db1ca932c62e453c37e00761628 from qemu
2018-02-20 18:46:01 +01:00
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
import
2015-08-21 09:04:50 +02:00
break;
target-i386: Implement CPUID[0xB] (Extended Topology Enumeration) I looked at a dozen Intel CPU that have this CPUID and all of them always had Core offset as 1 (a wasted bit when hyperthreading is disabled) and Package offset at least 4 (wasted bits at <= 4 cores). QEMU uses more compact IDs and it doesn't make much sense to change it now. I keep the SMT and Core sub-leaves even if there is just one thread/core; it makes the code simpler and there should be no harm. Backports commit 5232d00a041c8f3628b3532ef35d703a1f0dac19 from qemu
2018-02-25 00:29:20 +01:00
case 0xB:
/* Extended Topology Enumeration Leaf */
if (!cpu->enable_cpuid_0xb) {
*eax = *ebx = *ecx = *edx = 0;
break;
}
*ecx = count & 0xff;
*edx = cpu->apic_id;
switch (count) {
case 0:
*eax = apicid_core_offset(smp_cores, smp_threads);
*ebx = smp_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_SMT;
break;
case 1:
*eax = apicid_pkg_offset(smp_cores, smp_threads);
*ebx = smp_cores * smp_threads;
*ecx |= CPUID_TOPOLOGY_LEVEL_CORE;
break;
default:
*eax = 0;
*ebx = 0;
*ecx |= CPUID_TOPOLOGY_LEVEL_INVALID;
}
assert(!(*eax & ~0x1f));
*ebx &= 0xffff; /* The count doesn't need to be reliable. */
break;
import
2015-08-21 09:04:50 +02:00
case 0xD: {
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
uint64_t ena_mask;
int i;
target-i386: Add XSAVE extension This includes XSAVE, XRSTOR, XGETBV, XSETBV, which are all related, as well as the associate cpuid bits. Backports commit 19dc85dba23c0db1ca932c62e453c37e00761628 from qemu
2018-02-20 18:46:01 +01:00
/* Processor Extended State */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) {
break;
}
target-i386: xsave: Calculate enabled components only once Instead of checking both env->features and ena_mask at two different places in the CPUID code, initialize ena_mask based on the features that are enabled for the CPU, and then clear unsupported bits based on kvm_arch_get_supported_cpuid(). The results should be exactly the same, but it will make it easier to move the mask calculation elsewhare, and reuse x86_cpu_filter_features() for the kvm_arch_get_supported_cpuid() check. Backports commit 4928cd6de6b4211a79f98c8dc39115be1e815c2b from qemu
2018-02-26 10:33:16 +01:00
ena_mask = (XSTATE_FP_MASK | XSTATE_SSE_MASK);
for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
const ExtSaveArea *esa = &x86_ext_save_areas[i];
if (env->features[esa->feature] & esa->bits) {
ena_mask |= (1ULL << i);
}
}
/* Unicorn: commented out
if (kvm_enabled()) {
KVMState *s = cs->kvm_state;
uint64_t kvm_mask = kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX);
kvm_mask <<= 32;
kvm_mask |= kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX);
ena_mask &= kvm_mask;
} */
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
if (count == 0) {
*ecx = 0x240;
for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
const ExtSaveArea *esa = &x86_ext_save_areas[i];
target-i386: xsave: Calculate enabled components only once Instead of checking both env->features and ena_mask at two different places in the CPUID code, initialize ena_mask based on the features that are enabled for the CPU, and then clear unsupported bits based on kvm_arch_get_supported_cpuid(). The results should be exactly the same, but it will make it easier to move the mask calculation elsewhare, and reuse x86_cpu_filter_features() for the kvm_arch_get_supported_cpuid() check. Backports commit 4928cd6de6b4211a79f98c8dc39115be1e815c2b from qemu
2018-02-26 10:33:16 +01:00
if ((ena_mask >> i) & 1) {
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
*ecx = MAX(*ecx, esa->offset + esa->size);
}
}
target-i386: xsave: Simplify CPUID[0xD,0].{EAX,EDX} calculation Instead of assigning individual bits in a loop, just copy the values from ena_mask. Backports commit 8057c621b1b17cbcb35fe67d1a09ada9055873a9 from qemu
2018-02-26 10:35:11 +01:00
*eax = ena_mask;
*edx = ena_mask >> 32;
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
*ebx = *ecx;
} else if (count == 1) {
*eax = env->features[FEAT_XSAVE];
} else if (count < ARRAY_SIZE(x86_ext_save_areas)) {
const ExtSaveArea *esa = &x86_ext_save_areas[count];
target-i386: xsave: Calculate enabled components only once Instead of checking both env->features and ena_mask at two different places in the CPUID code, initialize ena_mask based on the features that are enabled for the CPU, and then clear unsupported bits based on kvm_arch_get_supported_cpuid(). The results should be exactly the same, but it will make it easier to move the mask calculation elsewhare, and reuse x86_cpu_filter_features() for the kvm_arch_get_supported_cpuid() check. Backports commit 4928cd6de6b4211a79f98c8dc39115be1e815c2b from qemu
2018-02-26 10:33:16 +01:00
if ((ena_mask >> count) & 1) {
target-i386: Enable control registers for MPX Enable and disable at CPL changes, MSR changes, and XRSTOR changes. Backports commit f4f1110e4b34797ddfa87bb28f9518b9256778be from qemu
2018-02-20 19:00:05 +01:00
*eax = esa->size;
*ebx = esa->offset;
}
}
import
2015-08-21 09:04:50 +02:00
break;
}
case 0x80000000:
*eax = env->cpuid_xlevel;
*ebx = env->cpuid_vendor1;
*edx = env->cpuid_vendor2;
*ecx = env->cpuid_vendor3;
break;
case 0x80000001:
*eax = env->cpuid_version;
*ebx = 0;
*ecx = env->features[FEAT_8000_0001_ECX];
*edx = env->features[FEAT_8000_0001_EDX];
/* The Linux kernel checks for the CMPLegacy bit and
* discards multiple thread information if it is set.
* So dont set it here for Intel to make Linux guests happy.
*/
if (cs->nr_cores * cs->nr_threads > 1) {
target-i386: Eliminate unnecessary get_cpuid_vendor() function The function was used in only two places. In one of them, the function made the code less readable by requiring temporary te[bcd]x variables. In the other one we can simply inline the existing code. Backports commit 08e1a1e5a175ecbfdb761db5a62090498f736969 from qemu
2018-02-12 21:25:31 +01:00
if (env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1 ||
env->cpuid_vendor2 != CPUID_VENDOR_INTEL_2 ||
env->cpuid_vendor3 != CPUID_VENDOR_INTEL_3) {
import
2015-08-21 09:04:50 +02:00
*ecx |= 1 << 1; /* CmpLegacy bit */
}
}
break;
case 0x80000002:
case 0x80000003:
case 0x80000004:
*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
break;
case 0x80000005:
/* cache info (L1 cache) */
if (cpu->cache_info_passthrough) {
host_cpuid(index, 0, eax, ebx, ecx, edx);
break;
}
*eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
*ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
(L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
*edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
(L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
break;
case 0x80000006:
/* cache info (L2 cache) */
if (cpu->cache_info_passthrough) {
host_cpuid(index, 0, eax, ebx, ecx, edx);
break;
}
*eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
(L2_DTLB_2M_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
(L2_ITLB_2M_ENTRIES);
*ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
(L2_DTLB_4K_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
(L2_ITLB_4K_ENTRIES);
*ecx = (L2_SIZE_KB_AMD << 16) | \
(AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
(L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
target-i386: present virtual L3 cache info for vcpus Some software algorithms are based on the hardware's cache info, for example, for x86 linux kernel, when cpu1 want to wakeup a task on cpu2, cpu1 will trigger a resched IPI and told cpu2 to do the wakeup if they don't share low level cache. Oppositely, cpu1 will access cpu2's runqueue directly if they share llc. The relevant linux-kernel code as bellow: static void ttwu_queue(struct task_struct *p, int cpu) { struct rq *rq = cpu_rq(cpu); ...... if (... && !cpus_share_cache(smp_processor_id(), cpu)) { ...... ttwu_queue_remote(p, cpu); /* will trigger RES IPI */ return; } ...... ttwu_do_activate(rq, p, 0); /* access target's rq directly */ ...... } In real hardware, the cpus on the same socket share L3 cache, so one won't trigger a resched IPIs when wakeup a task on others. But QEMU doesn't present a virtual L3 cache info for VM, then the linux guest will trigger lots of RES IPIs under some workloads even if the virtual cpus belongs to the same virtual socket. For KVM, there will be lots of vmexit due to guest send IPIs. The workload is a SAP HANA's testsuite, we run it one round(about 40 minuates) and observe the (Suse11sp3)Guest's amounts of RES IPIs which triggering during the period: No-L3 With-L3(applied this patch) cpu0: 363890 44582 cpu1: 373405 43109 cpu2: 340783 43797 cpu3: 333854 43409 cpu4: 327170 40038 cpu5: 325491 39922 cpu6: 319129 42391 cpu7: 306480 41035 cpu8: 161139 32188 cpu9: 164649 31024 cpu10: 149823 30398 cpu11: 149823 32455 cpu12: 164830 35143 cpu13: 172269 35805 cpu14: 179979 33898 cpu15: 194505 32754 avg: 268963.6 40129.8 The VM's topology is "1*socket 8*cores 2*threads". After present virtual L3 cache info for VM, the amounts of RES IPIs in guest reduce 85%. For KVM, vcpus send IPIs will cause vmexit which is expensive, so it can cause severe performance degradation. We had tested the overall system performance if vcpus actually run on sparate physical socket. With L3 cache, the performance improves 7.2%~33.1%(avg:15.7%). Backports commit 14c985cffa6cb177fc01a163d8bcf227c104718c from qemu
2018-02-26 05:16:03 +01:00
if (!cpu->enable_l3_cache) {
*edx = ((L3_SIZE_KB / 512) << 18) | \
(AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
(L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
} else {
*edx = ((L3_N_SIZE_KB_AMD / 512) << 18) | \
(AMD_ENC_ASSOC(L3_N_ASSOCIATIVITY) << 12) | \
(L3_N_LINES_PER_TAG << 8) | (L3_N_LINE_SIZE);
}
import
2015-08-21 09:04:50 +02:00
break;
case 0x80000007:
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = env->features[FEAT_8000_0007_EDX];
break;
case 0x80000008:
/* virtual & phys address size in low 2 bytes. */
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
target-i386: Allow physical address bits to be set Currently QEMU sets the x86 number of physical address bits to the magic number 40. This is only correct on some small AMD systems; Intel systems tend to have 36, 39, 46 bits, and large AMD systems tend to have 48. Having the value different from your actual hardware is detectable by the guest and in principal can cause problems; The current limit of 40 stops TB VMs being created by those lucky enough to have that much. This patch lets you set the physical bits by a cpu property but defaults to the same 40bits which matches TCGs setup. I've removed the ancient warning about the 42 bit limit in exec.c; I can't find that limit in there and no one else seems to know where it is. We use a magic value of 0 as the property default so that we can later distinguish between the default and a user set value. Backports commit af45907a132857cfd47acc998bf5f7c26cd13071 from qemu
2018-02-26 02:25:32 +01:00
/* 64 bit processor, 48 bits virtual, configurable
* physical bits.
*/
*eax = 0x00003000 + cpu->phys_bits;
import
2015-08-21 09:04:50 +02:00
} else {
target-i386: Allow physical address bits to be set Currently QEMU sets the x86 number of physical address bits to the magic number 40. This is only correct on some small AMD systems; Intel systems tend to have 36, 39, 46 bits, and large AMD systems tend to have 48. Having the value different from your actual hardware is detectable by the guest and in principal can cause problems; The current limit of 40 stops TB VMs being created by those lucky enough to have that much. This patch lets you set the physical bits by a cpu property but defaults to the same 40bits which matches TCGs setup. I've removed the ancient warning about the 42 bit limit in exec.c; I can't find that limit in there and no one else seems to know where it is. We use a magic value of 0 as the property default so that we can later distinguish between the default and a user set value. Backports commit af45907a132857cfd47acc998bf5f7c26cd13071 from qemu
2018-02-26 02:25:32 +01:00
*eax = cpu->phys_bits;
import
2015-08-21 09:04:50 +02:00
}
*ebx = 0;
*ecx = 0;
*edx = 0;
if (cs->nr_cores * cs->nr_threads > 1) {
*ecx |= (cs->nr_cores * cs->nr_threads) - 1;
}
break;
case 0x8000000A:
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
*eax = 0x00000001; /* SVM Revision */
*ebx = 0x00000010; /* nr of ASIDs */
*ecx = 0;
*edx = env->features[FEAT_SVM]; /* optional features */
} else {
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
}
break;
case 0xC0000000:
*eax = env->cpuid_xlevel2;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
case 0xC0000001:
/* Support for VIA CPU's CPUID instruction */
*eax = env->cpuid_version;
*ebx = 0;
*ecx = 0;
*edx = env->features[FEAT_C000_0001_EDX];
break;
case 0xC0000002:
case 0xC0000003:
case 0xC0000004:
/* Reserved for the future, and now filled with zero */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
default:
/* reserved values: zero */
*eax = 0;
*ebx = 0;
*ecx = 0;
*edx = 0;
break;
}
}
/* CPUClass::reset() */
static void x86_cpu_reset(CPUState *s)
{
X86CPU *cpu = X86_CPU(s->uc, s);
X86CPUClass *xcc = X86_CPU_GET_CLASS(s->uc, cpu);
CPUX86State *env = &cpu->env;
int i;
target-i386: Enable CR4/XCR0 features for user-mode Backports commit a114d25d5b42600871d75929604c0b9fcc448ec0 from qemu
2018-02-20 20:37:30 +01:00
target_ulong cr4;
uint64_t xcr0;
import
2015-08-21 09:04:50 +02:00
xcc->parent_reset(s);
target-i386: Add a marker to end of the region zeroed on reset Instead of using cpuid_level, use an empty struct as a marker (like we already did with {start,end}_init_save). This will avoid accidentaly resetting the wrong fields if we change the field ordering on CPUX86State. Backports commit 5e992a8e337e710ea2d02f35668ac55a80e15f99 from qemu
2018-02-26 09:58:08 +01:00
memset(env, 0, offsetof(CPUX86State, end_reset_fields));
import
2015-08-21 09:04:50 +02:00
tlb_flush(s, 1);
env->old_exception = -1;
/* init to reset state */
env->hflags2 |= HF2_GIF_MASK;
cpu_x86_update_cr0(env, 0x60000010);
env->a20_mask = ~0x0;
env->smbase = 0x30000;
env->idt.limit = 0xffff;
env->gdt.limit = 0xffff;
env->ldt.limit = 0xffff;
env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
env->tr.limit = 0xffff;
env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
DESC_R_MASK | DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
DESC_A_MASK);
env->eip = 0xfff0;
env->regs[R_EDX] = env->cpuid_version;
env->eflags = 0x2;
/* FPU init */
for (i = 0; i < 8; i++) {
env->fptags[i] = 1;
}
cpu_set_fpuc(env, 0x37f);
env->mxcsr = 0x1f80;
target-i386: Enable CR4/XCR0 features for user-mode Backports commit a114d25d5b42600871d75929604c0b9fcc448ec0 from qemu
2018-02-20 20:37:30 +01:00
/* All units are in INIT state. */
env->xstate_bv = 0;
import
2015-08-21 09:04:50 +02:00
env->pat = 0x0007040600070406ULL;
env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
memset(env->dr, 0, sizeof(env->dr));
env->dr[6] = DR6_FIXED_1;
env->dr[7] = DR7_FIXED_1;
cpu_breakpoint_remove_all(s, BP_CPU);
cpu_watchpoint_remove_all(s, BP_CPU);
target-i386: Enable CR4/XCR0 features for user-mode Backports commit a114d25d5b42600871d75929604c0b9fcc448ec0 from qemu
2018-02-20 20:37:30 +01:00
cr4 = 0;
target-i386: fix confusion in xcr0 bit position vs. mask The xsave and xrstor helpers are accessing the x86_ext_save_areas array using a bit mask instead of a bit position. Provide two sets of XSTATE_* definitions and use XSTATE_*_BIT when a bit position is requested. Backports commit cfc3b074de4b4ccee2540edbf8cfdb026dc19943 from qemu
2018-02-21 02:59:22 +01:00
xcr0 = XSTATE_FP_MASK;
target-i386: Enable CR4/XCR0 features for user-mode Backports commit a114d25d5b42600871d75929604c0b9fcc448ec0 from qemu
2018-02-20 20:37:30 +01:00
#ifdef CONFIG_USER_ONLY
/* Enable all the features for user-mode. */
if (env->features[FEAT_1_EDX] & CPUID_SSE) {
target-i386: fix confusion in xcr0 bit position vs. mask The xsave and xrstor helpers are accessing the x86_ext_save_areas array using a bit mask instead of a bit position. Provide two sets of XSTATE_* definitions and use XSTATE_*_BIT when a bit position is requested. Backports commit cfc3b074de4b4ccee2540edbf8cfdb026dc19943 from qemu
2018-02-21 02:59:22 +01:00
xcr0 |= XSTATE_SSE_MASK;
target-i386: Enable CR4/XCR0 features for user-mode Backports commit a114d25d5b42600871d75929604c0b9fcc448ec0 from qemu
2018-02-20 20:37:30 +01:00
}
target-i386: implement PKE for TCG Backports commit 0f70ed4759a29ca932af1e9525729f4f455642f8 from qemu
2018-02-22 16:18:48 +01:00
for (i = 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) {
const ExtSaveArea *esa = &x86_ext_save_areas[i];
target-i386: Don't try to enable PT State xsave component The code that calculates the set of supported XSAVE components on CPUID looks at ext_save_areas to find out which components should be enabled. However, if there are zeroed entries in the ext_save_areas array, the ((env->features[esa->feature] & esa->bits) == esa->bits) check will always succeed and QEMU will unconditionally try to enable the component. Luckily this never caused any problems because the only missing entry in ext_save_areas is the PT State component (bit 8), and KVM currently doesn't support it (so it was cleared on ena_mask). But the code was still incorrect and would break if KVM starts returning CPUID[EAX=0xD,ECX=0].EAX[bit 8] as supported on GET_SUPPORTED_CPUID. Fix the problem by changing the code to not enable a XSAVE component if ExtSaveArea::bits is zero. Backports commit 9646f4927faf68e8690588c2fd6dc9834c440b58 from qemu
2018-02-26 10:30:30 +01:00
if (env->features[esa->feature] & esa->bits) {
target-i386: implement PKE for TCG Backports commit 0f70ed4759a29ca932af1e9525729f4f455642f8 from qemu
2018-02-22 16:18:48 +01:00
xcr0 |= 1ull << i;
}
target-i386: Enable CR4/XCR0 features for user-mode Backports commit a114d25d5b42600871d75929604c0b9fcc448ec0 from qemu
2018-02-20 20:37:30 +01:00
}
target-i386: implement PKE for TCG Backports commit 0f70ed4759a29ca932af1e9525729f4f455642f8 from qemu
2018-02-22 16:18:48 +01:00
target-i386: Enable CR4/XCR0 features for user-mode Backports commit a114d25d5b42600871d75929604c0b9fcc448ec0 from qemu
2018-02-20 20:37:30 +01:00
if (env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) {
cr4 |= CR4_OSFXSR_MASK | CR4_OSXSAVE_MASK;
}
target-i386: Implement FSGSBASE Backports commit 07929f2ab2ab9c9e01d4ae79f48f2b2476b715c8 from qemu
2018-02-20 20:42:19 +01:00
if (env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_FSGSBASE) {
cr4 |= CR4_FSGSBASE_MASK;
}
target-i386: Enable CR4/XCR0 features for user-mode Backports commit a114d25d5b42600871d75929604c0b9fcc448ec0 from qemu
2018-02-20 20:37:30 +01:00
#endif
env->xcr0 = xcr0;
cpu_x86_update_cr4(env, cr4);
import
2015-08-21 09:04:50 +02:00
/*
* SDM 11.11.5 requires:
* - IA32_MTRR_DEF_TYPE MSR.E = 0
* - IA32_MTRR_PHYSMASKn.V = 0
* All other bits are undefined. For simplification, zero it all.
*/
env->mtrr_deftype = 0;
memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
#if !defined(CONFIG_USER_ONLY)
/* We hard-wire the BSP to the first CPU. */
target-i386: clear bsp bit when designating bsp Since the BSP bit is writable on real hardware, during reset all the CPUs which were not chosen to be the BSP should have their BSP bit cleared. This fix is required for KVM to work correctly when it changes the BSP bit. An additional fix is required for QEMU tcg to allow software to change the BSP bit. Backports commit 9cb11fd7539b5b787d8fb3834004804a58dd16ae from qemu
2018-02-12 22:38:52 +01:00
apic_designate_bsp(env->uc, cpu->apic_state, s->cpu_index == 0);
import
2015-08-21 09:04:50 +02:00
s->halted = !cpu_is_bsp(cpu);
#endif
}
#ifndef CONFIG_USER_ONLY
bool cpu_is_bsp(X86CPU *cpu)
{
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
return (cpu_get_apic_base((&cpu->env)->uc, cpu->apic_state) & MSR_IA32_APICBASE_BSP) != 0;
import
2015-08-21 09:04:50 +02:00
}
#endif
static void mce_init(X86CPU *cpu)
{
CPUX86State *cenv = &cpu->env;
unsigned int bank;
if (((cenv->cpuid_version >> 8) & 0xf) >= 6
&& (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
(CPUID_MCE | CPUID_MCA)) {
target-i386: kvm: Add basic Intel LMCE support This patch adds the support to inject SRAR and SRAO as LMCE, i.e. they are injected to only one VCPU rather than broadcast to all VCPUs. As KVM reports LMCE support on Intel platforms, this features is only available on Intel platforms. LMCE is disabled by default and can be enabled/disabled by cpu option 'lmce=on/off'. Backports commit 87f8b626041ceaea9adcfdbd549359f0ca7b871d from qemu
2018-02-25 08:48:14 +01:00
cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF |
(cpu->enable_lmce ? MCG_LMCE_P : 0);
import
2015-08-21 09:04:50 +02:00
cenv->mcg_ctl = ~(uint64_t)0;
for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
cenv->mce_banks[bank * 4] = ~(uint64_t)0;
}
}
}
#ifndef CONFIG_USER_ONLY
static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
{
#if 0
DeviceState *dev = DEVICE(cpu);
APICCommonState *apic;
const char *apic_type = "apic";
cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
if (cpu->apic_state == NULL) {
error_setg(errp, "APIC device '%s' could not be created", apic_type);
return;
}
target-i386: cpu: Do not ignore error and fix apic parent object_property_add_child() silently fails with error that it can't create duplicate propery 'apic' as we already have 'apic' property registered for 'apic' feature. As result generic device_realize puts apic into unattached container. As it's programming error, abort if name collision happens in future and fix property name for apic_state to 'lapic', this way apic is a child of cpu instance. Backports commit 6816b1b3811e839540df22855d975b6d76ae438b from qemu
2018-02-26 02:47:43 +01:00
object_property_add_child(OBJECT(cpu), "lapic",
OBJECT(cpu->apic_state), &error_abort);
target-i386: Fix apic object leak when CPU is deleted Backports commit 67e55caa6dcb91c80428cee6fe463f8dd8a755ab from qemu
2018-02-26 02:48:38 +01:00
object_unref(OBJECT(cpu->apic_state));
target-i386: Move CPUX86State.cpuid_apic_id to X86CPU.apic_id The field doesn't need to be inside CPUState, and it is not specific for the CPUID instruction, so move and rename it. Backports commit 9e9d3863adcbd1ffeca30f240f49805b00ba0d87 from qemu
2018-02-12 21:41:30 +01:00
//qdev_prop_set_uint8(cpu->apic_state, "id", cpu->apic_id);
import
2015-08-21 09:04:50 +02:00
/* TODO: convert to link<> */
apic = APIC_COMMON(cpu->apic_state);
apic->cpu = cpu;
#endif
}
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
{
if (cpu->apic_state == NULL) {
return;
}
if (qdev_init(cpu->apic_state)) {
error_setg(errp, "APIC device '%s' could not be initialized",
object_get_typename(OBJECT(cpu->apic_state)));
return;
}
}
#else
static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
{
}
#endif
target-i386: Set physical address bits based on host Add the host-phys-bits boolean property, if true, take phys-bits from the hosts physical bits value, overriding either the default or the user specified value. We can also use the value we read from the host to check the users explicitly set value and warn them if it doesn't match. Note: a) We only read the hosts value in KVM mode (because on non-x86 we get an abort if we try) b) We don't warn about trying to use host-phys-bits in TCG mode, we just fall back to the TCG default. This allows the machine type to set the host-phys-bits flag if it wants and then to work in both TCG and KVM. Backports commit 11f6fee576680a2d482123535da920f8ceb33eb5 from qemu
2018-02-26 02:34:46 +01:00
/* Note: Only safe for use on x86(-64) hosts */
static QEMU_UNUSED_FUNC uint32_t x86_host_phys_bits(void)
{
uint32_t eax;
uint32_t host_phys_bits;
host_cpuid(0x80000000, 0, &eax, NULL, NULL, NULL);
if (eax >= 0x80000008) {
host_cpuid(0x80000008, 0, &eax, NULL, NULL, NULL);
/* Note: According to AMD doc 25481 rev 2.34 they have a field
* at 23:16 that can specify a maximum physical address bits for
* the guest that can override this value; but I've not seen
* anything with that set.
*/
host_phys_bits = eax & 0xff;
} else {
/* It's an odd 64 bit machine that doesn't have the leaf for
* physical address bits; fall back to 36 that's most older
* Intel.
*/
host_phys_bits = 36;
}
return host_phys_bits;
}
import
2015-08-21 09:04:50 +02:00
target-i386: Automatically set level/xlevel/xlevel2 when needed Instead of requiring users and management software to be aware of required CPUID level/xlevel/xlevel2 values for each feature, automatically increase those values when features need them. This was already done for CPUID[7].EBX, and is now made generic for all CPUID feature flags. Unit test included, to make sure we don't break ABI on older machine-types and don't mess with the CPUID level values if they are explicitly set by the user. Backports commit c39c0edf9bb3b968ba95484465a50c7b19f4aa3a from qemu
2018-02-26 10:03:02 +01:00
static void x86_cpu_adjust_level(X86CPU *cpu, uint32_t *min, uint32_t value)
{
if (*min < value) {
*min = value;
}
}
/* Increase cpuid_min_{level,xlevel,xlevel2} automatically, if appropriate */
static void x86_cpu_adjust_feat_level(X86CPU *cpu, FeatureWord w)
{
CPUX86State *env = &cpu->env;
FeatureWordInfo *fi = &feature_word_info[w];
uint32_t eax = fi->cpuid_eax;
uint32_t region = eax & 0xF0000000;
if (!env->features[w]) {
return;
}
switch (region) {
case 0x00000000:
x86_cpu_adjust_level(cpu, &env->cpuid_min_level, eax);
break;
case 0x80000000:
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, eax);
break;
case 0xC0000000:
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel2, eax);
break;
}
}
import
2015-08-21 09:04:50 +02:00
#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_INTEL_1 && \
(env)->cpuid_vendor2 == CPUID_VENDOR_INTEL_2 && \
(env)->cpuid_vendor3 == CPUID_VENDOR_INTEL_3)
#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 == CPUID_VENDOR_AMD_1 && \
(env)->cpuid_vendor2 == CPUID_VENDOR_AMD_2 && \
(env)->cpuid_vendor3 == CPUID_VENDOR_AMD_3)
handle some errors properly so avoid exit() during initialization. this fixes issue #237
2015-11-11 18:43:41 +01:00
static int x86_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **errp)
import
2015-08-21 09:04:50 +02:00
{
CPUState *cs = CPU(dev);
X86CPU *cpu = X86_CPU(uc, dev);
X86CPUClass *xcc = X86_CPU_GET_CLASS(uc, dev);
CPUX86State *env = &cpu->env;
Error *local_err = NULL;
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
FeatureWord w;
import
2015-08-21 09:04:50 +02:00
target-i386: Use uint32_t for X86CPU.apic_id Redo 9886e834 (target-i386: Require APIC ID to be explicitly set before CPU realize) in another way that doesn't use int64_t to detect if apic-id property has been set. Use the fact that 0xFFFFFFFF is the broadcast value that a CPU can't have and set default uint32_t apic_id to it instead of using int64_t. Later uint32_t apic_id will be used to drop custom property setter/getter in favor of static property. Backports commit d9c84f196970f78d4b55ab87e03cbcad7c65f86f from qemu
2018-02-26 02:30:24 +01:00
if (cpu->apic_id == UNASSIGNED_APIC_ID) {
target-i386: Require APIC ID to be explicitly set before CPU realize Instead of setting APIC ID automatically when creating a X86CPU, require the property to be set before realizing the object (which all callers of cpu_x86_create() already do). Backports commit e1356dd70aef11425883dd4d2885f1d208eb9d57 from qemu
2018-02-12 21:48:11 +01:00
error_setg(errp, "apic-id property was not initialized properly");
return -1;
}
target-i386: Automatically set level/xlevel/xlevel2 when needed Instead of requiring users and management software to be aware of required CPUID level/xlevel/xlevel2 values for each feature, automatically increase those values when features need them. This was already done for CPUID[7].EBX, and is now made generic for all CPUID feature flags. Unit test included, to make sure we don't break ABI on older machine-types and don't mess with the CPUID level values if they are explicitly set by the user. Backports commit c39c0edf9bb3b968ba95484465a50c7b19f4aa3a from qemu
2018-02-26 10:03:02 +01:00
/* CPUID[EAX=7,ECX=0].EBX always increased level automatically: */
x86_cpu_adjust_feat_level(cpu, FEAT_7_0_EBX);
if (cpu->full_cpuid_auto_level) {
x86_cpu_adjust_feat_level(cpu, FEAT_1_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_1_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_6_EAX);
x86_cpu_adjust_feat_level(cpu, FEAT_7_0_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0001_ECX);
x86_cpu_adjust_feat_level(cpu, FEAT_8000_0007_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_C000_0001_EDX);
x86_cpu_adjust_feat_level(cpu, FEAT_SVM);
x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE);
target-i386: Enable CPUID[0x8000000A] if SVM is enabled SVM needs CPUID[0x8000000A] to be available. So if SVM is enabled in a CPU model or explicitly in the command-line, adjust CPUID xlevel to expose the CPUID[0x8000000A] leaf. Backports commit 0c3d7c0051576d220e6da0a8ac08f2d8482e2f0b from qemu
2018-02-26 10:05:44 +01:00
/* SVM requires CPUID[0x8000000A] */
if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
x86_cpu_adjust_level(cpu, &env->cpuid_min_xlevel, 0x8000000A);
}
target-i386: Automatically set level/xlevel/xlevel2 when needed Instead of requiring users and management software to be aware of required CPUID level/xlevel/xlevel2 values for each feature, automatically increase those values when features need them. This was already done for CPUID[7].EBX, and is now made generic for all CPUID feature flags. Unit test included, to make sure we don't break ABI on older machine-types and don't mess with the CPUID level values if they are explicitly set by the user. Backports commit c39c0edf9bb3b968ba95484465a50c7b19f4aa3a from qemu
2018-02-26 10:03:02 +01:00
}
/* Set cpuid_*level* based on cpuid_min_*level, if not explicitly set */
if (env->cpuid_level == UINT32_MAX) {
env->cpuid_level = env->cpuid_min_level;
}
if (env->cpuid_xlevel == UINT32_MAX) {
env->cpuid_xlevel = env->cpuid_min_xlevel;
}
if (env->cpuid_xlevel2 == UINT32_MAX) {
env->cpuid_xlevel2 = env->cpuid_min_xlevel2;
import
2015-08-21 09:04:50 +02:00
}
target-i386: Move features logic that requires CPUState to realize time Making x86_cpu_parse_featurestr() a pure convertor of legacy feature string into global properties, needs it to be called before a CPU instance is created so parser shouldn't modify CPUState directly or access it at all. Hence move current hack that directly pokes into CPUState, to set/unset +-feats, from parser to CPU's realize method. Backports commit dc15c0517b010a9444a2c05794dae980f2a2cbd9 from qemu
2018-02-25 00:44:40 +01:00
/*TODO: cpu->host_features incorrectly overwrites features
* set using "feat=on|off". Once we fix this, we can convert
* plus_features & minus_features to global properties
* inside x86_cpu_parse_featurestr() too.
*/
if (cpu->host_features) {
for (w = 0; w < FEATURE_WORDS; w++) {
env->features[w] =
x86_cpu_get_supported_feature_word(uc, w, cpu->migratable);
}
}
for (w = 0; w < FEATURE_WORDS; w++) {
cpu->env.features[w] |= cpu->plus_features[w];
cpu->env.features[w] &= ~cpu->minus_features[w];
}
import
2015-08-21 09:04:50 +02:00
/* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
* CPUID[1].EDX.
*/
if (IS_AMD_CPU(env)) {
env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
& CPUID_EXT2_AMD_ALIASES);
}
target-i386: Set physical address bits based on host Add the host-phys-bits boolean property, if true, take phys-bits from the hosts physical bits value, overriding either the default or the user specified value. We can also use the value we read from the host to check the users explicitly set value and warn them if it doesn't match. Note: a) We only read the hosts value in KVM mode (because on non-x86 we get an abort if we try) b) We don't warn about trying to use host-phys-bits in TCG mode, we just fall back to the TCG default. This allows the machine type to set the host-phys-bits flag if it wants and then to work in both TCG and KVM. Backports commit 11f6fee576680a2d482123535da920f8ceb33eb5 from qemu
2018-02-26 02:34:46 +01:00
/* For 64bit systems think about the number of physical bits to present.
* ideally this should be the same as the host; anything other than matching
* the host can cause incorrect guest behaviour.
* QEMU used to pick the magic value of 40 bits that corresponds to
* consumer AMD devices but nothing else.
*/
target-i386: Allow physical address bits to be set Currently QEMU sets the x86 number of physical address bits to the magic number 40. This is only correct on some small AMD systems; Intel systems tend to have 36, 39, 46 bits, and large AMD systems tend to have 48. Having the value different from your actual hardware is detectable by the guest and in principal can cause problems; The current limit of 40 stops TB VMs being created by those lucky enough to have that much. This patch lets you set the physical bits by a cpu property but defaults to the same 40bits which matches TCGs setup. I've removed the ancient warning about the 42 bit limit in exec.c; I can't find that limit in there and no one else seems to know where it is. We use a magic value of 0 as the property default so that we can later distinguish between the default and a user set value. Backports commit af45907a132857cfd47acc998bf5f7c26cd13071 from qemu
2018-02-26 02:25:32 +01:00
if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
// Unicorn: removed KVM checks
target-i386: Set physical address bits based on host Add the host-phys-bits boolean property, if true, take phys-bits from the hosts physical bits value, overriding either the default or the user specified value. We can also use the value we read from the host to check the users explicitly set value and warn them if it doesn't match. Note: a) We only read the hosts value in KVM mode (because on non-x86 we get an abort if we try) b) We don't warn about trying to use host-phys-bits in TCG mode, we just fall back to the TCG default. This allows the machine type to set the host-phys-bits flag if it wants and then to work in both TCG and KVM. Backports commit 11f6fee576680a2d482123535da920f8ceb33eb5 from qemu
2018-02-26 02:34:46 +01:00
if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
target-i386: Allow physical address bits to be set Currently QEMU sets the x86 number of physical address bits to the magic number 40. This is only correct on some small AMD systems; Intel systems tend to have 36, 39, 46 bits, and large AMD systems tend to have 48. Having the value different from your actual hardware is detectable by the guest and in principal can cause problems; The current limit of 40 stops TB VMs being created by those lucky enough to have that much. This patch lets you set the physical bits by a cpu property but defaults to the same 40bits which matches TCGs setup. I've removed the ancient warning about the 42 bit limit in exec.c; I can't find that limit in there and no one else seems to know where it is. We use a magic value of 0 as the property default so that we can later distinguish between the default and a user set value. Backports commit af45907a132857cfd47acc998bf5f7c26cd13071 from qemu
2018-02-26 02:25:32 +01:00
error_setg(errp, "TCG only supports phys-bits=%u",
TCG_PHYS_ADDR_BITS);
return -1;
}
target-i386: Set physical address bits based on host Add the host-phys-bits boolean property, if true, take phys-bits from the hosts physical bits value, overriding either the default or the user specified value. We can also use the value we read from the host to check the users explicitly set value and warn them if it doesn't match. Note: a) We only read the hosts value in KVM mode (because on non-x86 we get an abort if we try) b) We don't warn about trying to use host-phys-bits in TCG mode, we just fall back to the TCG default. This allows the machine type to set the host-phys-bits flag if it wants and then to work in both TCG and KVM. Backports commit 11f6fee576680a2d482123535da920f8ceb33eb5 from qemu
2018-02-26 02:34:46 +01:00
/* 0 means it was not explicitly set by the user (or by machine
* compat_props or by the host code above). In this case, the default
* is the value used by TCG (40).
*/
if (cpu->phys_bits == 0) {
cpu->phys_bits = TCG_PHYS_ADDR_BITS;
}
target-i386: Allow physical address bits to be set Currently QEMU sets the x86 number of physical address bits to the magic number 40. This is only correct on some small AMD systems; Intel systems tend to have 36, 39, 46 bits, and large AMD systems tend to have 48. Having the value different from your actual hardware is detectable by the guest and in principal can cause problems; The current limit of 40 stops TB VMs being created by those lucky enough to have that much. This patch lets you set the physical bits by a cpu property but defaults to the same 40bits which matches TCGs setup. I've removed the ancient warning about the 42 bit limit in exec.c; I can't find that limit in there and no one else seems to know where it is. We use a magic value of 0 as the property default so that we can later distinguish between the default and a user set value. Backports commit af45907a132857cfd47acc998bf5f7c26cd13071 from qemu
2018-02-26 02:25:32 +01:00
} else {
/* For 32 bit systems don't use the user set value, but keep
* phys_bits consistent with what we tell the guest.
*/
if (cpu->phys_bits != 0) {
error_setg(errp, "phys-bits is not user-configurable in 32 bit");
return -1;
}
if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
cpu->phys_bits = 36;
} else {
cpu->phys_bits = 32;
}
}
import
2015-08-21 09:04:50 +02:00
if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
error_setg(&local_err,
"TCG doesn't support requested features");
goto out;
}
target-i386: Move TCG initialization to realize time QOM instance_init functions are not supposed to have any side-effects, as new objects may be created at any moment for querying property information (see qmp_device_list_properties()). Move TCG initialization to realize time so it won't be called when just doing object_new() on a X86CPU subclass. Backports commit 57f2453ab48a771b30aeced01b329ee85853bb7b from qemu
2018-02-24 09:23:04 +01:00
if (tcg_enabled(env->uc)) {
tcg_x86_init(env->uc);
}
import
2015-08-21 09:04:50 +02:00
#ifndef CONFIG_USER_ONLY
//qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
x86_cpu_apic_create(cpu, &local_err);
if (local_err != NULL) {
goto out;
}
}
#endif
mce_init(cpu);
target-i386: create a separate AddressSpace for each CPU Different CPUs can be in SMM or not at the same time, thus they will see different things where the chipset places SMRAM. Backports commit 2001d0cd6d55e5efa9956fa8ff8b89034d6a4329 from qemu
2018-02-13 18:34:42 +01:00
#ifndef CONFIG_USER_ONLY
if (tcg_enabled(uc)) {
exec.c: Don't set cpu->as until cpu_address_space_init Rather than setting cpu->as unconditionally in cpu_exec_init (and then having target-i386 override this later), don't set it until the first call to cpu_address_space_init. This requires us to initialise the address space for both TCG and KVM (KVM doesn't need the AS listener but it does require cpu->as to be set). For target CPUs which don't set up any address spaces (currently everything except i386), add the default address_space_memory in qemu_init_vcpu(). Backports commit 56943e8cc14b7eeeab67d1942fa5d8bcafe3e53f from qemu
2018-02-18 03:54:06 +01:00
AddressSpace *newas = g_new(AddressSpace, 1);
target-i386: create a separate AddressSpace for each CPU Different CPUs can be in SMM or not at the same time, thus they will see different things where the chipset places SMRAM. Backports commit 2001d0cd6d55e5efa9956fa8ff8b89034d6a4329 from qemu
2018-02-13 18:34:42 +01:00
cpu->cpu_as_root = g_new(MemoryRegion, 1);
memory_region_init_alias(uc, cpu->cpu_as_root, OBJECT(cpu), "memory",
get_system_memory(uc), 0, ~0ull);
memory_region_set_enabled(cpu->cpu_as_root, true);
exec.c: Allow target CPUs to define multiple AddressSpaces Allow multiple calls to cpu_address_space_init(); each call adds an entry to the cpu->ases array at the specified index. It is up to the target-specific CPU code to actually use these extra address spaces. Since this multiple AddressSpace support won't work with KVM, add an assertion to avoid confusing failures. Backports commit 12ebc9a76dd7702aef0a3618717a826c19c34ef4 from qemu
2018-02-18 04:33:49 +01:00
cs->num_ases = 1;
exec.c: Don't set cpu->as until cpu_address_space_init Rather than setting cpu->as unconditionally in cpu_exec_init (and then having target-i386 override this later), don't set it until the first call to cpu_address_space_init. This requires us to initialise the address space for both TCG and KVM (KVM doesn't need the AS listener but it does require cpu->as to be set). For target CPUs which don't set up any address spaces (currently everything except i386), add the default address_space_memory in qemu_init_vcpu(). Backports commit 56943e8cc14b7eeeab67d1942fa5d8bcafe3e53f from qemu
2018-02-18 03:54:06 +01:00
address_space_init(uc, newas, cpu->cpu_as_root, "CPU");
cpu_address_space_init(cs, newas, 0);
target-i386: create a separate AddressSpace for each CPU Different CPUs can be in SMM or not at the same time, thus they will see different things where the chipset places SMRAM. Backports commit 2001d0cd6d55e5efa9956fa8ff8b89034d6a4329 from qemu
2018-02-13 18:34:42 +01:00
}
#endif
handle some errors properly so avoid exit() during initialization. this fixes issue #237
2015-11-11 18:43:41 +01:00
if (qemu_init_vcpu(cs))
return -1;
import
2015-08-21 09:04:50 +02:00
x86_cpu_apic_realize(cpu, &local_err);
if (local_err != NULL) {
goto out;
}
cpu_reset(cs);
xcc->parent_realize(uc, dev, &local_err);
out:
if (local_err != NULL) {
error_propagate(errp, local_err);
handle some errors properly so avoid exit() during initialization. this fixes issue #237
2015-11-11 18:43:41 +01:00
return -1;
import
2015-08-21 09:04:50 +02:00
}
handle some errors properly so avoid exit() during initialization. this fixes issue #237
2015-11-11 18:43:41 +01:00
return 0;
import
2015-08-21 09:04:50 +02:00
}
target-i386: Add x86_cpu_unrealizefn() First remove VCPU from exec loop and only then remove lapic. Backports commit c884776e9dc947105827bd6c22192863f97267d2 from qemu
2018-02-26 02:51:31 +01:00
static void x86_cpu_unrealizefn(struct uc_struct *uc, DeviceState *dev, Error **errp)
{
/* Unicorn: commented out
X86CPU *cpu = X86_CPU(uc, dev);
#ifndef CONFIG_USER_ONLY
cpu_remove_sync(CPU(dev));
qemu_unregister_reset(x86_cpu_machine_reset_cb, dev);
#endif
if (cpu->apic_state) {
object_unparent(OBJECT(cpu->apic_state));
cpu->apic_state = NULL;
}*/
}
import
2015-08-21 09:04:50 +02:00
static void x86_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
{
Automated leading tab to spaces conversion.
2017-01-21 02:28:22 +01:00
//printf("... X86 initialize (object)\n");
import
2015-08-21 09:04:50 +02:00
CPUState *cs = CPU(obj);
X86CPU *cpu = X86_CPU(cs->uc, obj);
X86CPUClass *xcc = X86_CPU_GET_CLASS(uc, obj);
CPUX86State *env = &cpu->env;
cs->env_ptr = env;
cpu: Change cpu_exec_init() arg to cpu, not env The callers (most of them in target-foo/cpu.c) to this function all have the cpu pointer handy. Just pass it to avoid an ENV_GET_CPU() from core code (in exec.c). Backports commit 4bad9e392e788a218967167a38ce2ae7a32a6231 from qemu
2018-02-14 20:13:43 +01:00
cpu_exec_init(cs, opaque);
import
2015-08-21 09:04:50 +02:00
qom: Allow properties to be registered against classes When there are many instances of a given class, registering properties against the instance is wasteful of resources. The majority of objects have a statically defined list of possible properties, so most of the properties are easily registerable against the class. Only those properties which are conditionally registered at runtime need be recorded against the klass. Registering properties against classes also makes it possible to provide static introspection of QOM - currently introspection is only possible after creating an instance of a class, which severely limits its usefulness. This impl only supports simple scalar properties. It does not attempt to allow child object / link object properties against the class. There are ways to support those too, but it would make this patch more complicated, so it is left as an exercise for the future. There is no equivalent to object_property_del() provided, since classes must be immutable once they are defined. Backports commit 16bf7f522a2ff68993f80631ed86254c71eaf5d4 from qemu
2018-02-21 19:58:46 +01:00
object_property_add(uc, obj, "family", "int",
import
2015-08-21 09:04:50 +02:00
x86_cpuid_version_get_family,
x86_cpuid_version_set_family, NULL, NULL, NULL);
qom: Allow properties to be registered against classes When there are many instances of a given class, registering properties against the instance is wasteful of resources. The majority of objects have a statically defined list of possible properties, so most of the properties are easily registerable against the class. Only those properties which are conditionally registered at runtime need be recorded against the klass. Registering properties against classes also makes it possible to provide static introspection of QOM - currently introspection is only possible after creating an instance of a class, which severely limits its usefulness. This impl only supports simple scalar properties. It does not attempt to allow child object / link object properties against the class. There are ways to support those too, but it would make this patch more complicated, so it is left as an exercise for the future. There is no equivalent to object_property_del() provided, since classes must be immutable once they are defined. Backports commit 16bf7f522a2ff68993f80631ed86254c71eaf5d4 from qemu
2018-02-21 19:58:46 +01:00
object_property_add(uc, obj, "model", "int",
import
2015-08-21 09:04:50 +02:00
x86_cpuid_version_get_model,
x86_cpuid_version_set_model, NULL, NULL, NULL);
qom: Allow properties to be registered against classes When there are many instances of a given class, registering properties against the instance is wasteful of resources. The majority of objects have a statically defined list of possible properties, so most of the properties are easily registerable against the class. Only those properties which are conditionally registered at runtime need be recorded against the klass. Registering properties against classes also makes it possible to provide static introspection of QOM - currently introspection is only possible after creating an instance of a class, which severely limits its usefulness. This impl only supports simple scalar properties. It does not attempt to allow child object / link object properties against the class. There are ways to support those too, but it would make this patch more complicated, so it is left as an exercise for the future. There is no equivalent to object_property_del() provided, since classes must be immutable once they are defined. Backports commit 16bf7f522a2ff68993f80631ed86254c71eaf5d4 from qemu
2018-02-21 19:58:46 +01:00
object_property_add(uc, obj, "stepping", "int",
import
2015-08-21 09:04:50 +02:00
x86_cpuid_version_get_stepping,
x86_cpuid_version_set_stepping, NULL, NULL, NULL);
qom: Allow properties to be registered against classes When there are many instances of a given class, registering properties against the instance is wasteful of resources. The majority of objects have a statically defined list of possible properties, so most of the properties are easily registerable against the class. Only those properties which are conditionally registered at runtime need be recorded against the klass. Registering properties against classes also makes it possible to provide static introspection of QOM - currently introspection is only possible after creating an instance of a class, which severely limits its usefulness. This impl only supports simple scalar properties. It does not attempt to allow child object / link object properties against the class. There are ways to support those too, but it would make this patch more complicated, so it is left as an exercise for the future. There is no equivalent to object_property_del() provided, since classes must be immutable once they are defined. Backports commit 16bf7f522a2ff68993f80631ed86254c71eaf5d4 from qemu
2018-02-21 19:58:46 +01:00
object_property_add_str(uc, obj, "vendor",
import
2015-08-21 09:04:50 +02:00
x86_cpuid_get_vendor,
x86_cpuid_set_vendor, NULL);
qom: Allow properties to be registered against classes When there are many instances of a given class, registering properties against the instance is wasteful of resources. The majority of objects have a statically defined list of possible properties, so most of the properties are easily registerable against the class. Only those properties which are conditionally registered at runtime need be recorded against the klass. Registering properties against classes also makes it possible to provide static introspection of QOM - currently introspection is only possible after creating an instance of a class, which severely limits its usefulness. This impl only supports simple scalar properties. It does not attempt to allow child object / link object properties against the class. There are ways to support those too, but it would make this patch more complicated, so it is left as an exercise for the future. There is no equivalent to object_property_del() provided, since classes must be immutable once they are defined. Backports commit 16bf7f522a2ff68993f80631ed86254c71eaf5d4 from qemu
2018-02-21 19:58:46 +01:00
object_property_add_str(uc, obj, "model-id",
import
2015-08-21 09:04:50 +02:00
x86_cpuid_get_model_id,
x86_cpuid_set_model_id, NULL);
qom: Allow properties to be registered against classes When there are many instances of a given class, registering properties against the instance is wasteful of resources. The majority of objects have a statically defined list of possible properties, so most of the properties are easily registerable against the class. Only those properties which are conditionally registered at runtime need be recorded against the klass. Registering properties against classes also makes it possible to provide static introspection of QOM - currently introspection is only possible after creating an instance of a class, which severely limits its usefulness. This impl only supports simple scalar properties. It does not attempt to allow child object / link object properties against the class. There are ways to support those too, but it would make this patch more complicated, so it is left as an exercise for the future. There is no equivalent to object_property_del() provided, since classes must be immutable once they are defined. Backports commit 16bf7f522a2ff68993f80631ed86254c71eaf5d4 from qemu
2018-02-21 19:58:46 +01:00
object_property_add(uc, obj, "tsc-frequency", "int",
import
2015-08-21 09:04:50 +02:00
x86_cpuid_get_tsc_freq,
x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
qom: Allow properties to be registered against classes When there are many instances of a given class, registering properties against the instance is wasteful of resources. The majority of objects have a statically defined list of possible properties, so most of the properties are easily registerable against the class. Only those properties which are conditionally registered at runtime need be recorded against the klass. Registering properties against classes also makes it possible to provide static introspection of QOM - currently introspection is only possible after creating an instance of a class, which severely limits its usefulness. This impl only supports simple scalar properties. It does not attempt to allow child object / link object properties against the class. There are ways to support those too, but it would make this patch more complicated, so it is left as an exercise for the future. There is no equivalent to object_property_del() provided, since classes must be immutable once they are defined. Backports commit 16bf7f522a2ff68993f80631ed86254c71eaf5d4 from qemu
2018-02-21 19:58:46 +01:00
object_property_add(uc, obj, "feature-words", "X86CPUFeatureWordInfo",
import
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x86_cpu_get_feature_words,
NULL, NULL, (void *)env->features, NULL);
qom: Allow properties to be registered against classes When there are many instances of a given class, registering properties against the instance is wasteful of resources. The majority of objects have a statically defined list of possible properties, so most of the properties are easily registerable against the class. Only those properties which are conditionally registered at runtime need be recorded against the klass. Registering properties against classes also makes it possible to provide static introspection of QOM - currently introspection is only possible after creating an instance of a class, which severely limits its usefulness. This impl only supports simple scalar properties. It does not attempt to allow child object / link object properties against the class. There are ways to support those too, but it would make this patch more complicated, so it is left as an exercise for the future. There is no equivalent to object_property_del() provided, since classes must be immutable once they are defined. Backports commit 16bf7f522a2ff68993f80631ed86254c71eaf5d4 from qemu
2018-02-21 19:58:46 +01:00
object_property_add(uc, obj, "filtered-features", "X86CPUFeatureWordInfo",
import
2015-08-21 09:04:50 +02:00
x86_cpu_get_feature_words,
NULL, NULL, (void *)cpu->filtered_features, NULL);
cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
target-i386: Replace custom apic-id setter/getter with static property Custom apic-id setter/getter doesn't do any property specific checks anymore, so clean it up and use more compact static property DEFINE_PROP_UINT32 instead. Backports commit 2da00e3176abac34ca7a6aab1f5bbb94a0d03fc5 from qemu
2018-02-26 02:41:24 +01:00
// Unicorn: Should be removed with the commit backporting 2da00e3176abac34ca7a6aab1f5bbb94a0d03fc5
// from qemu, but left this in to keep the member value initialized
target-i386: Use uint32_t for X86CPU.apic_id Redo 9886e834 (target-i386: Require APIC ID to be explicitly set before CPU realize) in another way that doesn't use int64_t to detect if apic-id property has been set. Use the fact that 0xFFFFFFFF is the broadcast value that a CPU can't have and set default uint32_t apic_id to it instead of using int64_t. Later uint32_t apic_id will be used to drop custom property setter/getter in favor of static property. Backports commit d9c84f196970f78d4b55ab87e03cbcad7c65f86f from qemu
2018-02-26 02:30:24 +01:00
cpu->apic_id = UNASSIGNED_APIC_ID;
import
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x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
}
static int64_t x86_cpu_get_arch_id(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs->uc, cs);
target-i386: Move CPUX86State.cpuid_apic_id to X86CPU.apic_id The field doesn't need to be inside CPUState, and it is not specific for the CPUID instruction, so move and rename it. Backports commit 9e9d3863adcbd1ffeca30f240f49805b00ba0d87 from qemu
2018-02-12 21:41:30 +01:00
return cpu->apic_id;
import
2015-08-21 09:04:50 +02:00
}
static bool x86_cpu_get_paging_enabled(const CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs->uc, cs);
This code should now build the x86_x64-softmmu part 2.
2017-01-19 12:50:28 +01:00
return (cpu->env.cr[0] & CR0_PG_MASK) != 0;
import
2015-08-21 09:04:50 +02:00
}
static void x86_cpu_set_pc(CPUState *cs, vaddr value)
{
X86CPU *cpu = X86_CPU(cs->uc, cs);
cpu->env.eip = value;
}
static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
{
X86CPU *cpu = X86_CPU(cs->uc, cs);
cpu->env.eip = tb->pc - tb->cs_base;
}
static bool x86_cpu_has_work(CPUState *cs)
{
X86CPU *cpu = X86_CPU(cs->uc, cs);
CPUX86State *env = &cpu->env;
#if !defined(CONFIG_USER_ONLY)
if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
apic_poll_irq(cpu->apic_state);
cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
}
#endif
return ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) ||
(cs->interrupt_request & (CPU_INTERRUPT_NMI |
CPU_INTERRUPT_INIT |
CPU_INTERRUPT_SIPI |
target-i386: wake up processors that receive an SMI An SMI should definitely wake up a processor in halted state! This lets OVMF boot with SMM on multiprocessor systems, although it halts very soon after that with a "CpuIndex != BspIndex" assertion failure. Backports commit a9bad65d2c1f61af74ce2ff43238d4b20bf81c3a from qemu
2018-02-13 18:31:59 +01:00
CPU_INTERRUPT_MCE)) ||
((cs->interrupt_request & CPU_INTERRUPT_SMI) &&
!(env->hflags & HF_SMM_MASK));
import
2015-08-21 09:04:50 +02:00
}
static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
{
Automated leading tab to spaces conversion.
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//printf("... init X86 cpu common class\n");
import
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X86CPUClass *xcc = X86_CPU_CLASS(uc, oc);
CPUClass *cc = CPU_CLASS(uc, oc);
DeviceClass *dc = DEVICE_CLASS(uc, oc);
xcc->parent_realize = dc->realize;
dc->realize = x86_cpu_realizefn;
target-i386: Add x86_cpu_unrealizefn() First remove VCPU from exec loop and only then remove lapic. Backports commit c884776e9dc947105827bd6c22192863f97267d2 from qemu
2018-02-26 02:51:31 +01:00
dc->unrealize = x86_cpu_unrealizefn;
import
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dc->bus_type = TYPE_ICC_BUS;
xcc->parent_reset = cc->reset;
cc->reset = x86_cpu_reset;
cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
cc->class_by_name = x86_cpu_class_by_name;
cc->parse_features = x86_cpu_parse_featurestr;
cc->has_work = x86_cpu_has_work;
cc->do_interrupt = x86_cpu_do_interrupt;
cc->cpu_exec_interrupt = x86_cpu_exec_interrupt;
cc->dump_state = x86_cpu_dump_state;
cc->set_pc = x86_cpu_set_pc;
cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
cc->get_arch_id = x86_cpu_get_arch_id;
cc->get_paging_enabled = x86_cpu_get_paging_enabled;
#ifdef CONFIG_USER_ONLY
cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
#else
cc->get_memory_mapping = x86_cpu_get_memory_mapping;
cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
#endif
#ifndef CONFIG_USER_ONLY
cc->debug_excp_handler = breakpoint_handler;
#endif
cc->cpu_exec_enter = x86_cpu_exec_enter;
cc->cpu_exec_exit = x86_cpu_exec_exit;
}
void x86_cpu_register_types(void *opaque)
{
Automated leading tab to spaces conversion.
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const TypeInfo x86_cpu_type_info = {
TYPE_X86_CPU,
TYPE_CPU,
cleanup after msvc port
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Automated leading tab to spaces conversion.
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sizeof(X86CPUClass),
sizeof(X86CPU),
opaque,
cleanup after msvc port
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Automated leading tab to spaces conversion.
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x86_cpu_initfn,
NULL,
NULL,
cleanup after msvc port
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Automated leading tab to spaces conversion.
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NULL,
x86_cpu_common_class_init,
NULL,
NULL,
cleanup after msvc port
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Automated leading tab to spaces conversion.
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true,
};
//printf("... register X86 cpu\n");
import
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int i;
type_register_static(opaque, &x86_cpu_type_info);
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
x86_register_cpudef_type(opaque, &builtin_x86_defs[i]);
}
Automated leading tab to spaces conversion.
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//printf("... END OF register X86 cpu\n");
import
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}
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