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target/arm: Correct exclusive store cmpxchg memop mask

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When we perform the atomic_cmpxchg operation we want to perform the
operation on a pair of 32-bit registers. Previously we were just passing
the register size in which was set to MO_32. This would result in the
high register to be ignored. To fix this issue we hardcode the size to
be 64-bits long when operating on 32-bit pairs.

Backports commit 955fd0ad5d610f62ba2f4ce46a872bf50434dcf8 from qemu
This commit is contained in:
Alistair Francis 2018-03-04 01:43:47 -05:00 committed by Lioncash
parent fd472c53c6
commit 009a52dd13
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1 changed files with 1 additions and 1 deletions
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qemu/target/arm/translate-a64.c
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@ -1959,7 +1959,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
tcg_gen_concat32_i64(tcg_ctx, val, tcg_ctx->cpu_exclusive_val, tcg_ctx->cpu_exclusive_high);
tcg_gen_atomic_cmpxchg_i64(tcg_ctx, tmp, addr, val, tmp,
get_mem_index(s),
size | MO_ALIGN | s->be_data);
MO_64 | MO_ALIGN | s->be_data);
tcg_gen_setcond_i64(tcg_ctx, TCG_COND_NE, tmp, tmp, val);
tcg_temp_free_i64(tcg_ctx, val);
} else if (s->be_data == MO_LE) {