From 00d06bf20e1894953d2b91cd051320f41ffc9dc3 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 20 Feb 2018 22:21:59 -0500 Subject: [PATCH] target-arm: In v8, make illegal AArch32 mode changes set PSTATE.IL In v8, the illegal mode changes which are UNPREDICTABLE in v7 are given architected behaviour: * the mode field is unchanged * PSTATE.IL is set (so any subsequent instructions will UNDEF) * any other CPSR fields are written to as normal This is pretty much the same behaviour we picked for our UNPREDICTABLE handling, with the exception that for v8 we need to set the IL bit. Backports commit 81907a582901671c15be36a63b5063f88f3487e2 from qemu --- qemu/target-arm/helper.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 21a91dd8..5120110d 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -4628,11 +4628,20 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask, (env->uncached_cpsr & CPSR_M) != CPSR_USER && ((env->uncached_cpsr ^ val) & mask & CPSR_M)) { if (bad_mode_switch(env, val & CPSR_M)) { - /* Attempt to switch to an invalid mode: this is UNPREDICTABLE. - * We choose to ignore the attempt and leave the CPSR M field - * untouched. + /* Attempt to switch to an invalid mode: this is UNPREDICTABLE in + * v7, and has defined behaviour in v8: + * + leave CPSR.M untouched + * + allow changes to the other CPSR fields + * + set PSTATE.IL + * For user changes via the GDB stub, we don't set PSTATE.IL, + * as this would be unnecessarily harsh for a user error. */ mask &= ~CPSR_M; + if (write_type != CPSRWriteByGDBStub && + arm_feature(env, ARM_FEATURE_V8)) { + mask |= CPSR_IL; + val |= CPSR_IL; + } } else { switch_mode(env, val & CPSR_M); }