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target-arm: Use clrsb helper

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Backports commit bc21dbcc1203ae6bb536f832c46a3b5e22a73451 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 18:16:40 -05:00 committed by Lioncash
parent fff7ca4617
commit 01b3c6273a
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GPG Key ID: 4E3C3CC1031BA9C7
6 changed files with 4 additions and 22 deletions
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2
qemu/aarch64.h
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@ -3426,8 +3426,6 @@
#define arm_regime_tbi1 arm_regime_tbi1_aarch64
#define arm_register_el_change_hook arm_register_el_change_hook_aarch64
#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64
#define helper_cls32 helper_cls32_aarch64
#define helper_cls64 helper_cls64_aarch64
#define helper_crc32_64 helper_crc32_64_aarch64
#define helper_crc32c_64 helper_crc32c_64_aarch64
#define helper_fcvtx_f64_to_f32 helper_fcvtx_f64_to_f32_aarch64

2
qemu/aarch64eb.h
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@ -3426,8 +3426,6 @@
#define arm_regime_tbi1 arm_regime_tbi1_aarch64eb
#define arm_register_el_change_hook arm_register_el_change_hook_aarch64eb
#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64eb
#define helper_cls32 helper_cls32_aarch64eb
#define helper_cls64 helper_cls64_aarch64eb
#define helper_crc32_64 helper_crc32_64_aarch64eb
#define helper_crc32c_64 helper_crc32c_64_aarch64eb
#define helper_fcvtx_f64_to_f32 helper_fcvtx_f64_to_f32_aarch64eb

2
qemu/header_gen.py
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@ -3442,8 +3442,6 @@ aarch64_symbols = (
'arm_regime_tbi1',
'arm_register_el_change_hook',
'gen_a64_set_pc_im',
'helper_cls32',
'helper_cls64',
'helper_crc32_64',
'helper_crc32c_64',
'helper_fcvtx_f64_to_f32',

10
qemu/target-arm/helper-a64.c
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@ -52,16 +52,6 @@ int64_t HELPER(sdiv64)(int64_t num, int64_t den)
return num / den;
}
uint64_t HELPER(cls64)(uint64_t x)
{
return clrsb64(x);
}
uint32_t HELPER(cls32)(uint32_t x)
{
return clrsb32(x);
}
uint64_t HELPER(rbit64)(uint64_t x)
{
return revbit64(x);

2
qemu/target-arm/helper-a64.h
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@ -18,8 +18,6 @@
*/
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
DEF_HELPER_FLAGS_1(cls64, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cls32, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)

8
qemu/target-arm/translate-a64.c
View File

@ -4044,11 +4044,11 @@ static void handle_cls(DisasContext *s, unsigned int sf,
tcg_rn = cpu_reg(s, rn);
if (sf) {
gen_helper_cls64(tcg_ctx, tcg_rd, tcg_rn);
tcg_gen_clrsb_i64(tcg_ctx, tcg_rd, tcg_rn);
} else {
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_tmp32, tcg_rn);
gen_helper_cls32(tcg_ctx, tcg_tmp32, tcg_tmp32);
tcg_gen_clrsb_i32(tcg_ctx, tcg_tmp32, tcg_tmp32);
tcg_gen_extu_i32_i64(tcg_ctx, tcg_rd, tcg_tmp32);
tcg_temp_free_i32(tcg_ctx, tcg_tmp32);
}
@ -7715,7 +7715,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
if (u) {
tcg_gen_clzi_i64(tcg_ctx, tcg_rd, tcg_rn, 64);
} else {
gen_helper_cls64(tcg_ctx, tcg_rd, tcg_rn);
tcg_gen_clrsb_i64(tcg_ctx, tcg_rd, tcg_rn);
}
break;
case 0x5: /* NOT */
@ -10409,7 +10409,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
if (u) {
tcg_gen_clzi_i32(tcg_ctx, tcg_res, tcg_op, 32);
} else {
gen_helper_cls32(tcg_ctx, tcg_res, tcg_op);
tcg_gen_clrsb_i32(tcg_ctx, tcg_res, tcg_op);
}
break;
case 0x7: /* SQABS, SQNEG */