mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-10-19 11:18:17 +02:00
target/arm: Use vector infrastructure for aa64 add/sub/logic
Backports commit bc48092f5865c20893bb19200a7a320feac99eeb from qemu
This commit is contained in:
parent
f30abaea66
commit
03b76589b4
@ -22,6 +22,7 @@
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#include "cpu.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/exec-all.h"
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#include "tcg-op.h"
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#include "tcg-op.h"
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#include "tcg-op-gvec.h"
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#include "qemu/log.h"
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#include "qemu/log.h"
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#include "arm_ldst.h"
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#include "arm_ldst.h"
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#include "translate.h"
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#include "translate.h"
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@ -81,6 +82,10 @@ typedef void CryptoTwoOpFn(TCGContext *, TCGv_ptr, TCGv_ptr);
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typedef void CryptoThreeOpIntFn(TCGContext *, TCGv_ptr, TCGv_ptr, TCGv_i32);
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typedef void CryptoThreeOpIntFn(TCGContext *, TCGv_ptr, TCGv_ptr, TCGv_i32);
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typedef void CryptoThreeOpFn(TCGContext *, TCGv_ptr, TCGv_ptr, TCGv_ptr);
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typedef void CryptoThreeOpFn(TCGContext *, TCGv_ptr, TCGv_ptr, TCGv_ptr);
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/* Note that the gvec expanders operate on offsets + sizes. */
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typedef void GVecGen3Fn(TCGContext *, unsigned, uint32_t, uint32_t,
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uint32_t, uint32_t, uint32_t);
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/* initialize TCG globals. */
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/* initialize TCG globals. */
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void a64_translate_init(struct uc_struct *uc)
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void a64_translate_init(struct uc_struct *uc)
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{
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{
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@ -577,6 +582,14 @@ static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno)
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return ret;
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return ret;
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}
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}
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/* Return the byte size of the "whole" vector register, VL / 8. */
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static inline int vec_full_reg_size(DisasContext *s)
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{
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/* FIXME SVE: We should put the composite ZCR_EL* value into tb->flags.
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In the meantime this is just the AdvSIMD length of 128. */
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return 128 / 8;
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}
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/* Return the offset into CPUARMState of a slice (from
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/* Return the offset into CPUARMState of a slice (from
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* the least significant end) of FP register Qn (ie
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* the least significant end) of FP register Qn (ie
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* Dn, Sn, Hn or Bn).
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* Dn, Sn, Hn or Bn).
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@ -651,6 +664,27 @@ static TCGv_ptr get_fpstatus_ptr(TCGContext *tcg_ctx)
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return statusptr;
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return statusptr;
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}
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}
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/* Expand a 3-operand AdvSIMD vector operation using an expander function. */
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static void gen_gvec_fn3(DisasContext *s, bool is_q, int rd, int rn, int rm,
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GVecGen3Fn *gvec_fn, int vece)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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gvec_fn(tcg_ctx, vece, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
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vec_full_reg_offset(s, rm), is_q ? 16 : 8, vec_full_reg_size(s));
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}
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/* Expand a 3-operand AdvSIMD vector operation using an op descriptor. */
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static void gen_gvec_op3(DisasContext *s, bool is_q, int rd,
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int rn, int rm, const GVecGen3 *gvec_op)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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tcg_gen_gvec_3(tcg_ctx, vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn),
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vec_full_reg_offset(s, rm), is_q ? 16 : 8,
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vec_full_reg_size(s), gvec_op);
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}
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/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
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/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
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* than the 32 bit equivalent.
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* than the 32 bit equivalent.
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*/
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*/
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@ -9203,86 +9237,109 @@ static void disas_simd_three_reg_diff(DisasContext *s, uint32_t insn)
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}
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}
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}
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}
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static void gen_bsl_i64(TCGContext *s, TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(s, rn, rn, rm);
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tcg_gen_and_i64(s, rn, rn, rd);
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tcg_gen_xor_i64(s, rd, rm, rn);
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}
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static void gen_bit_i64(TCGContext *s, TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(s, rn, rn, rd);
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tcg_gen_and_i64(s, rn, rn, rm);
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tcg_gen_xor_i64(s, rd, rd, rn);
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}
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static void gen_bif_i64(TCGContext *s, TCGv_i64 rd, TCGv_i64 rn, TCGv_i64 rm)
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{
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tcg_gen_xor_i64(s, rn, rn, rd);
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tcg_gen_andc_i64(s, rn, rn, rm);
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tcg_gen_xor_i64(s, rd, rd, rn);
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}
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static void gen_bsl_vec(TCGContext *s, unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(s, vece, rn, rn, rm);
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tcg_gen_and_vec(s, vece, rn, rn, rd);
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tcg_gen_xor_vec(s, vece, rd, rm, rn);
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}
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static void gen_bit_vec(TCGContext *s, unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(s, vece, rn, rn, rd);
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tcg_gen_and_vec(s, vece, rn, rn, rm);
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tcg_gen_xor_vec(s, vece, rd, rd, rn);
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}
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static void gen_bif_vec(TCGContext *s, unsigned vece, TCGv_vec rd, TCGv_vec rn, TCGv_vec rm)
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{
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tcg_gen_xor_vec(s, vece, rn, rn, rd);
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tcg_gen_andc_vec(s, vece, rn, rn, rm);
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tcg_gen_xor_vec(s, vece, rd, rd, rn);
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}
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/* Logic op (opcode == 3) subgroup of C3.6.16. */
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/* Logic op (opcode == 3) subgroup of C3.6.16. */
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static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
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static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
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{
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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static const GVecGen3 bsl_op = {
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.fni8 = gen_bsl_i64,
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.fniv = gen_bsl_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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static const GVecGen3 bit_op = {
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.fni8 = gen_bit_i64,
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.fniv = gen_bit_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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static const GVecGen3 bif_op = {
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.fni8 = gen_bif_i64,
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.fniv = gen_bif_vec,
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.prefer_i64 = TCG_TARGET_REG_BITS == 64,
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.load_dest = true
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};
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int rd = extract32(insn, 0, 5);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int rn = extract32(insn, 5, 5);
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int rm = extract32(insn, 16, 5);
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int rm = extract32(insn, 16, 5);
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int size = extract32(insn, 22, 2);
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int size = extract32(insn, 22, 2);
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bool is_u = extract32(insn, 29, 1);
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bool is_u = extract32(insn, 29, 1);
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bool is_q = extract32(insn, 30, 1);
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bool is_q = extract32(insn, 30, 1);
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TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
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int pass;
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if (!fp_access_check(s)) {
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if (!fp_access_check(s)) {
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return;
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return;
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}
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}
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tcg_op1 = tcg_temp_new_i64(tcg_ctx);
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switch (size + 4 * is_u) {
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tcg_op2 = tcg_temp_new_i64(tcg_ctx);
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case 0: /* AND */
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tcg_res[0] = tcg_temp_new_i64(tcg_ctx);
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_and, 0);
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tcg_res[1] = tcg_temp_new_i64(tcg_ctx);
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return;
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case 1: /* BIC */
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for (pass = 0; pass < (is_q ? 2 : 1); pass++) {
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0);
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read_vec_element(s, tcg_op1, rn, pass, MO_64);
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return;
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read_vec_element(s, tcg_op2, rm, pass, MO_64);
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case 2: /* ORR */
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
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if (!is_u) {
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return;
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switch (size) {
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case 3: /* ORN */
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case 0: /* AND */
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0);
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tcg_gen_and_i64(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2);
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return;
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break;
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case 4: /* EOR */
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case 1: /* BIC */
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_xor, 0);
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tcg_gen_andc_i64(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2);
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return;
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break;
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case 5: /* BSL bitwise select */
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case 2: /* ORR */
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gen_gvec_op3(s, is_q, rd, rn, rm, &bsl_op);
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tcg_gen_or_i64(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2);
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return;
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break;
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case 6: /* BIT, bitwise insert if true */
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case 3: /* ORN */
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gen_gvec_op3(s, is_q, rd, rn, rm, &bit_op);
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tcg_gen_orc_i64(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2);
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return;
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break;
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case 7: /* BIF, bitwise insert if false */
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}
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gen_gvec_op3(s, is_q, rd, rn, rm, &bif_op);
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} else {
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return;
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if (size != 0) {
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default:
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/* B* ops need res loaded to operate on */
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g_assert_not_reached();
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read_vec_element(s, tcg_res[pass], rd, pass, MO_64);
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}
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switch (size) {
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case 0: /* EOR */
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tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2);
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break;
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case 1: /* BSL bitwise select */
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tcg_gen_xor_i64(tcg_ctx, tcg_op1, tcg_op1, tcg_op2);
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tcg_gen_and_i64(tcg_ctx, tcg_op1, tcg_op1, tcg_res[pass]);
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tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_op2, tcg_op1);
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break;
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case 2: /* BIT, bitwise insert if true */
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tcg_gen_xor_i64(tcg_ctx, tcg_op1, tcg_op1, tcg_res[pass]);
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tcg_gen_and_i64(tcg_ctx, tcg_op1, tcg_op1, tcg_op2);
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tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_res[pass], tcg_op1);
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break;
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case 3: /* BIF, bitwise insert if false */
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tcg_gen_xor_i64(tcg_ctx, tcg_op1, tcg_op1, tcg_res[pass]);
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tcg_gen_andc_i64(tcg_ctx, tcg_op1, tcg_op1, tcg_op2);
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tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_res[pass], tcg_op1);
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break;
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}
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}
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}
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}
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write_vec_element(s, tcg_res[0], rd, 0, MO_64);
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if (!is_q) {
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tcg_gen_movi_i64(tcg_ctx, tcg_res[1], 0);
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}
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write_vec_element(s, tcg_res[1], rd, 1, MO_64);
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tcg_temp_free_i64(tcg_ctx, tcg_op1);
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tcg_temp_free_i64(tcg_ctx, tcg_op2);
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tcg_temp_free_i64(tcg_ctx, tcg_res[0]);
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tcg_temp_free_i64(tcg_ctx, tcg_res[1]);
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}
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}
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/* Helper functions for 32 bit comparisons */
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/* Helper functions for 32 bit comparisons */
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@ -9584,6 +9641,16 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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return;
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return;
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}
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}
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switch (opcode) {
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case 0x10: /* ADD, SUB */
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if (u) {
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size);
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} else {
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_add, size);
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}
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return;
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}
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if (size == 3) {
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if (size == 3) {
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assert(is_q);
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assert(is_q);
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for (pass = 0; pass < 2; pass++) {
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for (pass = 0; pass < 2; pass++) {
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@ -9756,16 +9823,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
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genfn = fns[size][u];
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genfn = fns[size][u];
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break;
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break;
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}
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}
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case 0x10: /* ADD, SUB */
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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{ gen_helper_neon_add_u8, gen_helper_neon_sub_u8 },
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{ gen_helper_neon_add_u16, gen_helper_neon_sub_u16 },
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{ tcg_gen_add_i32, tcg_gen_sub_i32 },
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};
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genfn = fns[size][u];
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break;
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}
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case 0x11: /* CMTST, CMEQ */
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case 0x11: /* CMTST, CMEQ */
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{
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{
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static NeonGenTwoOpFn * const fns[3][2] = {
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static NeonGenTwoOpFn * const fns[3][2] = {
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