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target/arm: Fix ISAR6 register state

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Lioncash 2018-07-03 19:31:50 -04:00
parent 0c6311f8cc
commit 0cf14f0d13
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1 changed files with 1 additions and 1 deletions
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qemu/target/arm/helper.c
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@ -4266,7 +4266,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar5 },
{ "ID_MMFR4", 0,0,2, 3,0,6, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL1_R, 0, NULL, cpu->id_mmfr4 },
{ "ID_ISAR6", 0,0,2, 3,0,7, 0,
{ "ID_ISAR6", 0,0,2, 3,0,7, ARM_CP_STATE_BOTH,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->id_isar6 },
REGINFO_SENTINEL
};