diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c
index 93ff0c0c..3132bd34 100644
--- a/qemu/target-mips/translate.c
+++ b/qemu/target-mips/translate.c
@@ -11196,7 +11196,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx)
         break;
 #if defined(TARGET_MIPS64)
     case M16_OPC_LD:
-            check_mips_64(ctx);
+        check_mips_64(ctx);
         gen_ld(ctx, OPC_LD, ry, rx, offset);
         break;
 #endif
@@ -18515,7 +18515,7 @@ static void hook_insn(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patc
     }
 }
 
-static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch, int *insn_patch_offset)
+static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_patch, int *insn_patch_offset)
 {
     TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
 #if defined(TARGET_MIPS64)
@@ -18684,7 +18684,8 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
                     save_cpu_state(ctx, 1);
                     gen_helper_di(tcg_ctx, t0, tcg_ctx->cpu_env);
                     gen_store_gpr(tcg_ctx, t0, rt);
-                    /* Stop translation as we may have switched the execution mode */
+                    /* Stop translation as we may have switched
+                       the execution mode */
                     ctx->bstate = BS_STOP;
                     break;
                 case OPC_EI:
@@ -18692,7 +18693,8 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
                     save_cpu_state(ctx, 1);
                     gen_helper_ei(tcg_ctx, t0, tcg_ctx->cpu_env);
                     gen_store_gpr(tcg_ctx, t0, rt);
-                    /* Stop translation as we may have switched the execution mode */
+                    /* Stop translation as we may have switched
+                       the execution mode */
                     ctx->bstate = BS_STOP;
                     break;
                 default:            /* Invalid */
@@ -18899,8 +18901,8 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
         case OPC_S_FMT:
         case OPC_D_FMT:
             check_cp1_enabled(ctx);
-            gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f), rt, rd, sa,
-                       (imm >> 8) & 0x7);
+            gen_farith(ctx, ctx->opcode & FOP(0x3f, 0x1f),
+                       rt, rd, sa, (imm >> 8) & 0x7);
             break;
         case OPC_W_FMT:
         case OPC_L_FMT:
diff --git a/qemu/target-mips/translate_init.c b/qemu/target-mips/translate_init.c
index 7a6a5344..088adc4f 100644
--- a/qemu/target-mips/translate_init.c
+++ b/qemu/target-mips/translate_init.c
@@ -861,33 +861,33 @@ static const mips_def_t mips_defs[] =
         MMU_TYPE_R4000,
     },
     {
-      "Loongson-2F",
-      0x6303,
-      /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
-      (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
+        "Loongson-2F",
+        0x6303,
+        /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
+        (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
                      (0x1<<4) | (0x1<<1),
-      /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
-      (1 << CP0C1_FP) | (47 << CP0C1_MMU),
-      0,
-      0,
-      0,0,
-      0,0,
-      0,
-      0,
-      0,
-      0,
-      16,
-      2,
-      0xF5D0FF1F,   /*bit5:7 not writable*/
-      0,
-      0,
-      (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
-      0,
-      40,
-      40,
-      0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
-      CPU_LOONGSON2F,
-      MMU_TYPE_R4000,
+        /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
+        (1 << CP0C1_FP) | (47 << CP0C1_MMU),
+        0,
+        0,
+        0,0,
+        0,0,
+        0,
+        0,
+        0,
+        0,
+        16,
+        2,
+        0xF5D0FF1F,   /*bit5:7 not writable*/
+        0,
+        0,
+        (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
+        0,
+        40,
+        40,
+        0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
+        CPU_LOONGSON2F,
+        MMU_TYPE_R4000,
     },
     {
         /* A generic CPU providing MIPS64 ASE DSP 2 features.