From 1001f0ba1ffdbeca2bdf0334289b5843360c818b Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Thu, 30 Apr 2020 06:19:39 -0400 Subject: [PATCH] target/riscv: Correctly implement TSR trap As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Backports commit ed5abf46b3c414ef58e647145f19b3966700b206 from qemu --- qemu/target/riscv/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/riscv/op_helper.c b/qemu/target/riscv/op_helper.c index 6e31656f..f00c59c7 100644 --- a/qemu/target/riscv/op_helper.c +++ b/qemu/target/riscv/op_helper.c @@ -84,7 +84,7 @@ target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) } if (env->priv_ver >= PRIV_VERSION_1_10_0 && - get_field(env->mstatus, MSTATUS_TSR)) { + get_field(env->mstatus, MSTATUS_TSR) && !(env->priv >= PRV_M)) { riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); }