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target-arm: Fix REVIDR reset value

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According to ARM Cortex-A53/A57 TRM, REVIDR reset value should be zero. So let
REVIDR reset value be specified by CPU model and correct it for Cortex-A53/A57.

Backports commit 13b72b2b9aa7ab7ee129e38e9587acd6a1b9a932 from qemu
This commit is contained in:
Sergey Fedorov 2018-02-13 14:22:43 -05:00 committed by Lioncash
parent f6d104b33a
commit 113cda90c3
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GPG Key ID: 4E3C3CC1031BA9C7
3 changed files with 5 additions and 3 deletions
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1
qemu/target-arm/cpu-qom.h
View File

@ -126,6 +126,7 @@ typedef struct ARMCPU {
* prefix means a constant register.
*/
uint32_t midr;
uint32_t revidr;
uint32_t reset_fpsid;
uint32_t mvfr0;
uint32_t mvfr1;

2
qemu/target-arm/cpu64.c
View File

@ -93,6 +93,7 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
set_feature(&cpu->env, ARM_FEATURE_PMU);
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
cpu->midr = 0x411fd070;
cpu->revidr = 0x00000000;
cpu->reset_fpsid = 0x41034070;
cpu->mvfr0 = 0x10110222;
cpu->mvfr1 = 0x12111111;
@ -143,6 +144,7 @@ static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC);
cpu->midr = 0x410fd034;
cpu->revidr = 0x00000000;
cpu->reset_fpsid = 0x41034070;
cpu->mvfr0 = 0x10110222;
cpu->mvfr1 = 0x12111111;

5
qemu/target-arm/helper.c
View File

@ -2938,13 +2938,12 @@ void register_cp_regs_for_features(ARMCPU *cpu)
};
ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
/* v8 MIDR -- the wildcard isn't necessary, and nor is the
* variable-MIDR TI925 behaviour. Instead we have a single
* (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
* variable-MIDR TI925 behaviour.
*/
{ "MIDR_EL1", 0,0,0, 3,0,0, ARM_CP_STATE_BOTH,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->midr },
{ "REVIDR_EL1", 0,0,0, 3,0,6, ARM_CP_STATE_BOTH,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->midr },
ARM_CP_CONST, PL1_R, 0, NULL, cpu->revidr },
REGINFO_SENTINEL
};
ARMCPRegInfo id_cp_reginfo[] = {