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target-sparc: Use explicit writes to cpu_fsr

Browse Source 
By arranging for explicit writes to cpu_fsr after floating point
operations, we are able to mark the helpers as not writing to
tcg globals, which means that we don't need to invalidate the
integer register set across said calls.

Backports commit 7385aed20db5d83979f683b9d0048674411e963c from qemu
This commit is contained in:
Richard Henderson 2018-02-25 18:40:53 -05:00 committed by Lioncash
parent 2e24c09db3
commit 12eecc4939
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
6 changed files with 402 additions and 447 deletions
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139
qemu/header_gen.py
View File

@ -4156,79 +4156,80 @@ mips_symbols = (
)
sparc_symbols = (
'cpu_sparc_exec',
'helper_compute_psr',
'helper_compute_C_icc',
'cpu_sparc_init',
'cpu_sparc_set_id',
'sparc_cpu_register_types',
'helper_fadds',
'helper_faddd',
'helper_faddq',
'helper_fsubs',
'helper_fsubd',
'helper_fsubq',
'helper_fmuls',
'helper_fmuld',
'helper_fmulq',
'helper_fdivs',
'helper_fdivd',
'helper_fdivq',
'helper_fsmuld',
'helper_fdmulq',
'helper_fnegs',
'helper_fitos',
'helper_fitod',
'helper_fitoq',
'helper_fdtos',
'helper_fstod',
'helper_fqtos',
'helper_fstoq',
'helper_fqtod',
'helper_fdtoq',
'helper_fstoi',
'helper_fdtoi',
'helper_fqtoi',
'helper_fabss',
'helper_fsqrts',
'helper_fsqrtd',
'helper_fsqrtq',
'helper_fcmps',
'helper_fcmpd',
'helper_fcmpes',
'helper_fcmped',
'helper_fcmpq',
'helper_fcmpeq',
'helper_ldfsr',
'helper_debug',
'helper_udiv_cc',
'helper_sdiv_cc',
'helper_taddcctv',
'helper_tsubcctv',
'sparc_cpu_do_interrupt',
'helper_check_align',
'helper_ld_asi',
'helper_st_asi',
'helper_cas_asi',
'helper_ldqf',
'helper_stqf',
'sparc_cpu_unassigned_access',
'sparc_cpu_do_unaligned_access',
'sparc_cpu_handle_mmu_fault',
'dump_mmu',
'sparc_cpu_get_phys_page_debug',
'sparc_reg_reset',
'sparc_reg_read',
'sparc_reg_write',
'gen_intermediate_code_init',
'cpu_set_cwp',
'cpu_cwp_dec',
'cpu_cwp_inc',
'cpu_get_psr',
'cpu_put_psr',
'cpu_put_psr_raw',
'cpu_cwp_inc',
'cpu_cwp_dec',
'cpu_set_cwp',
'cpu_sparc_exec',
'cpu_sparc_init',
'cpu_sparc_set_id',
'dump_mmu',
'gen_intermediate_code_init',
'helper_cas_asi',
'helper_check_align',
'helper_check_ieee_exceptions',
'helper_compute_C_icc',
'helper_compute_psr',
'helper_debug',
'helper_fabss',
'helper_faddd',
'helper_faddq',
'helper_fadds',
'helper_fcmpd',
'helper_fcmped',
'helper_fcmpeq',
'helper_fcmpes',
'helper_fcmpq',
'helper_fcmps',
'helper_fdivd',
'helper_fdivq',
'helper_fdivs',
'helper_fdmulq',
'helper_fdtoi',
'helper_fdtoq',
'helper_fdtos',
'helper_fitod',
'helper_fitoq',
'helper_fitos',
'helper_fmuld',
'helper_fmulq',
'helper_fmuls',
'helper_fnegs',
'helper_fqtod',
'helper_fqtoi',
'helper_fqtos',
'helper_fsmuld',
'helper_fsqrtd',
'helper_fsqrtq',
'helper_fsqrts',
'helper_fstod',
'helper_fstoi',
'helper_fstoq',
'helper_fsubd',
'helper_fsubq',
'helper_fsubs',
'helper_ld_asi',
'helper_ldfsr',
'helper_ldqf',
'helper_restore',
'helper_save',
'helper_restore')
'helper_sdiv_cc',
'helper_st_asi',
'helper_stqf',
'helper_taddcctv',
'helper_tsubcctv',
'helper_udiv_cc',
'sparc_cpu_do_interrupt',
'sparc_cpu_do_unaligned_access',
'sparc_cpu_get_phys_page_debug',
'sparc_cpu_handle_mmu_fault',
'sparc_cpu_register_types',
'sparc_cpu_unassigned_access',
'sparc_reg_read',
'sparc_reg_reset',
'sparc_reg_write')
if __name__ == '__main__':

140
qemu/sparc.h
View File

@ -3147,77 +3147,77 @@
#define xpsr_write xpsr_write_sparc
#define xscale_cpar_write xscale_cpar_write_sparc
#define xscale_cp_reginfo xscale_cp_reginfo_sparc
#define cpu_sparc_exec cpu_sparc_exec_sparc
#define helper_compute_psr helper_compute_psr_sparc
#define helper_compute_C_icc helper_compute_C_icc_sparc
#define cpu_sparc_init cpu_sparc_init_sparc
#define cpu_sparc_set_id cpu_sparc_set_id_sparc
#define sparc_cpu_register_types sparc_cpu_register_types_sparc
#define helper_fadds helper_fadds_sparc
#define helper_faddd helper_faddd_sparc
#define helper_faddq helper_faddq_sparc
#define helper_fsubs helper_fsubs_sparc
#define helper_fsubd helper_fsubd_sparc
#define helper_fsubq helper_fsubq_sparc
#define helper_fmuls helper_fmuls_sparc
#define helper_fmuld helper_fmuld_sparc
#define helper_fmulq helper_fmulq_sparc
#define helper_fdivs helper_fdivs_sparc
#define helper_fdivd helper_fdivd_sparc
#define helper_fdivq helper_fdivq_sparc
#define helper_fsmuld helper_fsmuld_sparc
#define helper_fdmulq helper_fdmulq_sparc
#define helper_fnegs helper_fnegs_sparc
#define helper_fitos helper_fitos_sparc
#define helper_fitod helper_fitod_sparc
#define helper_fitoq helper_fitoq_sparc
#define helper_fdtos helper_fdtos_sparc
#define helper_fstod helper_fstod_sparc
#define helper_fqtos helper_fqtos_sparc
#define helper_fstoq helper_fstoq_sparc
#define helper_fqtod helper_fqtod_sparc
#define helper_fdtoq helper_fdtoq_sparc
#define helper_fstoi helper_fstoi_sparc
#define helper_fdtoi helper_fdtoi_sparc
#define helper_fqtoi helper_fqtoi_sparc
#define helper_fabss helper_fabss_sparc
#define helper_fsqrts helper_fsqrts_sparc
#define helper_fsqrtd helper_fsqrtd_sparc
#define helper_fsqrtq helper_fsqrtq_sparc
#define helper_fcmps helper_fcmps_sparc
#define helper_fcmpd helper_fcmpd_sparc
#define helper_fcmpes helper_fcmpes_sparc
#define helper_fcmped helper_fcmped_sparc
#define helper_fcmpq helper_fcmpq_sparc
#define helper_fcmpeq helper_fcmpeq_sparc
#define helper_ldfsr helper_ldfsr_sparc
#define helper_debug helper_debug_sparc
#define helper_udiv_cc helper_udiv_cc_sparc
#define helper_sdiv_cc helper_sdiv_cc_sparc
#define helper_taddcctv helper_taddcctv_sparc
#define helper_tsubcctv helper_tsubcctv_sparc
#define sparc_cpu_do_interrupt sparc_cpu_do_interrupt_sparc
#define helper_check_align helper_check_align_sparc
#define helper_ld_asi helper_ld_asi_sparc
#define helper_st_asi helper_st_asi_sparc
#define helper_cas_asi helper_cas_asi_sparc
#define helper_ldqf helper_ldqf_sparc
#define helper_stqf helper_stqf_sparc
#define sparc_cpu_unassigned_access sparc_cpu_unassigned_access_sparc
#define sparc_cpu_do_unaligned_access sparc_cpu_do_unaligned_access_sparc
#define sparc_cpu_handle_mmu_fault sparc_cpu_handle_mmu_fault_sparc
#define dump_mmu dump_mmu_sparc
#define sparc_cpu_get_phys_page_debug sparc_cpu_get_phys_page_debug_sparc
#define sparc_reg_reset sparc_reg_reset_sparc
#define sparc_reg_read sparc_reg_read_sparc
#define sparc_reg_write sparc_reg_write_sparc
#define gen_intermediate_code_init gen_intermediate_code_init_sparc
#define cpu_set_cwp cpu_set_cwp_sparc
#define cpu_cwp_dec cpu_cwp_dec_sparc
#define cpu_cwp_inc cpu_cwp_inc_sparc
#define cpu_get_psr cpu_get_psr_sparc
#define cpu_put_psr cpu_put_psr_sparc
#define cpu_put_psr_raw cpu_put_psr_raw_sparc
#define cpu_cwp_inc cpu_cwp_inc_sparc
#define cpu_cwp_dec cpu_cwp_dec_sparc
#define helper_save helper_save_sparc
#define helper_restore helper_restore_sparc
#define cpu_set_cwp cpu_set_cwp_sparc
#define cpu_sparc_exec cpu_sparc_exec_sparc
#define cpu_sparc_init cpu_sparc_init_sparc
#define cpu_sparc_set_id cpu_sparc_set_id_sparc
#define dump_mmu dump_mmu_sparc
#define gen_intermediate_code_init gen_intermediate_code_init_sparc
#define helper_cas_asi helper_cas_asi_sparc
#define helper_check_align helper_check_align_sparc
#define helper_check_ieee_exception helper_check_ieee_exception_sparc
#define helper_compute_C_icc helper_compute_C_icc_sparc
#define helper_compute_psr helper_compute_psr_sparc
#define helper_debug helper_debug_sparc
#define helper_fabss helper_fabss_sparc
#define helper_faddd helper_faddd_sparc
#define helper_faddq helper_faddq_sparc
#define helper_fadds helper_fadds_sparc
#define helper_fcmpd helper_fcmpd_sparc
#define helper_fcmped helper_fcmped_sparc
#define helper_fcmpeq helper_fcmpeq_sparc
#define helper_fcmpes helper_fcmpes_sparc
#define helper_fcmpq helper_fcmpq_sparc
#define helper_fcmps helper_fcmps_sparc
#define helper_fdivd helper_fdivd_sparc
#define helper_fdivq helper_fdivq_sparc
#define helper_fdivs helper_fdivs_sparc
#define helper_fdmulq helper_fdmulq_sparc
#define helper_fdtoi helper_fdtoi_sparc
#define helper_fdtoq helper_fdtoq_sparc
#define helper_fdtos helper_fdtos_sparc
#define helper_fitod helper_fitod_sparc
#define helper_fitoq helper_fitoq_sparc
#define helper_fitos helper_fitos_sparc
#define helper_fmuld helper_fmuld_sparc
#define helper_fmulq helper_fmulq_sparc
#define helper_fmuls helper_fmuls_sparc
#define helper_fnegs helper_fnegs_sparc
#define helper_fqtod helper_fqtod_sparc
#define helper_fqtoi helper_fqtoi_sparc
#define helper_fqtos helper_fqtos_sparc
#define helper_fsmuld helper_fsmuld_sparc
#define helper_fsqrtd helper_fsqrtd_sparc
#define helper_fsqrtq helper_fsqrtq_sparc
#define helper_fsqrts helper_fsqrts_sparc
#define helper_fstod helper_fstod_sparc
#define helper_fstoi helper_fstoi_sparc
#define helper_fstoq helper_fstoq_sparc
#define helper_fsubd helper_fsubd_sparc
#define helper_fsubq helper_fsubq_sparc
#define helper_fsubs helper_fsubs_sparc
#define helper_ld_asi helper_ld_asi_sparc
#define helper_ldfsr helper_ldfsr_sparc
#define helper_ldqf helper_ldqf_sparc
#define helper_restorehelper_save helper_restorehelper_save_sparc
#define helper_sdiv_cc helper_sdiv_cc_sparc
#define helper_st_asi helper_st_asi_sparc
#define helper_stqf helper_stqf_sparc
#define helper_taddcctv helper_taddcctv_sparc
#define helper_tsubcctv helper_tsubcctv_sparc
#define helper_udiv_cc helper_udiv_cc_sparc
#define sparc_cpu_do_interrupt sparc_cpu_do_interrupt_sparc
#define sparc_cpu_do_unaligned_access sparc_cpu_do_unaligned_access_sparc
#define sparc_cpu_get_phys_page_debug sparc_cpu_get_phys_page_debug_sparc
#define sparc_cpu_handle_mmu_fault sparc_cpu_handle_mmu_fault_sparc
#define sparc_cpu_register_types sparc_cpu_register_types_sparc
#define sparc_cpu_unassigned_access sparc_cpu_unassigned_access_sparc
#define sparc_reg_read sparc_reg_read_sparc
#define sparc_reg_reset sparc_reg_reset_sparc
#define sparc_reg_write sparc_reg_write_sparc
#endif

140
qemu/sparc64.h
View File

@ -3147,77 +3147,77 @@
#define xpsr_write xpsr_write_sparc64
#define xscale_cpar_write xscale_cpar_write_sparc64
#define xscale_cp_reginfo xscale_cp_reginfo_sparc64
#define cpu_sparc_exec cpu_sparc_exec_sparc64
#define helper_compute_psr helper_compute_psr_sparc64
#define helper_compute_C_icc helper_compute_C_icc_sparc64
#define cpu_sparc_init cpu_sparc_init_sparc64
#define cpu_sparc_set_id cpu_sparc_set_id_sparc64
#define sparc_cpu_register_types sparc_cpu_register_types_sparc64
#define helper_fadds helper_fadds_sparc64
#define helper_faddd helper_faddd_sparc64
#define helper_faddq helper_faddq_sparc64
#define helper_fsubs helper_fsubs_sparc64
#define helper_fsubd helper_fsubd_sparc64
#define helper_fsubq helper_fsubq_sparc64
#define helper_fmuls helper_fmuls_sparc64
#define helper_fmuld helper_fmuld_sparc64
#define helper_fmulq helper_fmulq_sparc64
#define helper_fdivs helper_fdivs_sparc64
#define helper_fdivd helper_fdivd_sparc64
#define helper_fdivq helper_fdivq_sparc64
#define helper_fsmuld helper_fsmuld_sparc64
#define helper_fdmulq helper_fdmulq_sparc64
#define helper_fnegs helper_fnegs_sparc64
#define helper_fitos helper_fitos_sparc64
#define helper_fitod helper_fitod_sparc64
#define helper_fitoq helper_fitoq_sparc64
#define helper_fdtos helper_fdtos_sparc64
#define helper_fstod helper_fstod_sparc64
#define helper_fqtos helper_fqtos_sparc64
#define helper_fstoq helper_fstoq_sparc64
#define helper_fqtod helper_fqtod_sparc64
#define helper_fdtoq helper_fdtoq_sparc64
#define helper_fstoi helper_fstoi_sparc64
#define helper_fdtoi helper_fdtoi_sparc64
#define helper_fqtoi helper_fqtoi_sparc64
#define helper_fabss helper_fabss_sparc64
#define helper_fsqrts helper_fsqrts_sparc64
#define helper_fsqrtd helper_fsqrtd_sparc64
#define helper_fsqrtq helper_fsqrtq_sparc64
#define helper_fcmps helper_fcmps_sparc64
#define helper_fcmpd helper_fcmpd_sparc64
#define helper_fcmpes helper_fcmpes_sparc64
#define helper_fcmped helper_fcmped_sparc64
#define helper_fcmpq helper_fcmpq_sparc64
#define helper_fcmpeq helper_fcmpeq_sparc64
#define helper_ldfsr helper_ldfsr_sparc64
#define helper_debug helper_debug_sparc64
#define helper_udiv_cc helper_udiv_cc_sparc64
#define helper_sdiv_cc helper_sdiv_cc_sparc64
#define helper_taddcctv helper_taddcctv_sparc64
#define helper_tsubcctv helper_tsubcctv_sparc64
#define sparc_cpu_do_interrupt sparc_cpu_do_interrupt_sparc64
#define helper_check_align helper_check_align_sparc64
#define helper_ld_asi helper_ld_asi_sparc64
#define helper_st_asi helper_st_asi_sparc64
#define helper_cas_asi helper_cas_asi_sparc64
#define helper_ldqf helper_ldqf_sparc64
#define helper_stqf helper_stqf_sparc64
#define sparc_cpu_unassigned_access sparc_cpu_unassigned_access_sparc64
#define sparc_cpu_do_unaligned_access sparc_cpu_do_unaligned_access_sparc64
#define sparc_cpu_handle_mmu_fault sparc_cpu_handle_mmu_fault_sparc64
#define dump_mmu dump_mmu_sparc64
#define sparc_cpu_get_phys_page_debug sparc_cpu_get_phys_page_debug_sparc64
#define sparc_reg_reset sparc_reg_reset_sparc64
#define sparc_reg_read sparc_reg_read_sparc64
#define sparc_reg_write sparc_reg_write_sparc64
#define gen_intermediate_code_init gen_intermediate_code_init_sparc64
#define cpu_set_cwp cpu_set_cwp_sparc64
#define cpu_cwp_dec cpu_cwp_dec_sparc64
#define cpu_cwp_inc cpu_cwp_inc_sparc64
#define cpu_get_psr cpu_get_psr_sparc64
#define cpu_put_psr cpu_put_psr_sparc64
#define cpu_put_psr_raw cpu_put_psr_raw_sparc64
#define cpu_cwp_inc cpu_cwp_inc_sparc64
#define cpu_cwp_dec cpu_cwp_dec_sparc64
#define helper_save helper_save_sparc64
#define helper_restore helper_restore_sparc64
#define cpu_set_cwp cpu_set_cwp_sparc64
#define cpu_sparc_exec cpu_sparc_exec_sparc64
#define cpu_sparc_init cpu_sparc_init_sparc64
#define cpu_sparc_set_id cpu_sparc_set_id_sparc64
#define dump_mmu dump_mmu_sparc64
#define gen_intermediate_code_init gen_intermediate_code_init_sparc64
#define helper_cas_asi helper_cas_asi_sparc64
#define helper_check_align helper_check_align_sparc64
#define helper_check_ieee_exception helper_check_ieee_exception_sparc64
#define helper_compute_C_icc helper_compute_C_icc_sparc64
#define helper_compute_psr helper_compute_psr_sparc64
#define helper_debug helper_debug_sparc64
#define helper_fabss helper_fabss_sparc64
#define helper_faddd helper_faddd_sparc64
#define helper_faddq helper_faddq_sparc64
#define helper_fadds helper_fadds_sparc64
#define helper_fcmpd helper_fcmpd_sparc64
#define helper_fcmped helper_fcmped_sparc64
#define helper_fcmpeq helper_fcmpeq_sparc64
#define helper_fcmpes helper_fcmpes_sparc64
#define helper_fcmpq helper_fcmpq_sparc64
#define helper_fcmps helper_fcmps_sparc64
#define helper_fdivd helper_fdivd_sparc64
#define helper_fdivq helper_fdivq_sparc64
#define helper_fdivs helper_fdivs_sparc64
#define helper_fdmulq helper_fdmulq_sparc64
#define helper_fdtoi helper_fdtoi_sparc64
#define helper_fdtoq helper_fdtoq_sparc64
#define helper_fdtos helper_fdtos_sparc64
#define helper_fitod helper_fitod_sparc64
#define helper_fitoq helper_fitoq_sparc64
#define helper_fitos helper_fitos_sparc64
#define helper_fmuld helper_fmuld_sparc64
#define helper_fmulq helper_fmulq_sparc64
#define helper_fmuls helper_fmuls_sparc64
#define helper_fnegs helper_fnegs_sparc64
#define helper_fqtod helper_fqtod_sparc64
#define helper_fqtoi helper_fqtoi_sparc64
#define helper_fqtos helper_fqtos_sparc64
#define helper_fsmuld helper_fsmuld_sparc64
#define helper_fsqrtd helper_fsqrtd_sparc64
#define helper_fsqrtq helper_fsqrtq_sparc64
#define helper_fsqrts helper_fsqrts_sparc64
#define helper_fstod helper_fstod_sparc64
#define helper_fstoi helper_fstoi_sparc64
#define helper_fstoq helper_fstoq_sparc64
#define helper_fsubd helper_fsubd_sparc64
#define helper_fsubq helper_fsubq_sparc64
#define helper_fsubs helper_fsubs_sparc64
#define helper_ld_asi helper_ld_asi_sparc64
#define helper_ldfsr helper_ldfsr_sparc64
#define helper_ldqf helper_ldqf_sparc64
#define helper_restorehelper_save helper_restorehelper_save_sparc64
#define helper_sdiv_cc helper_sdiv_cc_sparc64
#define helper_st_asi helper_st_asi_sparc64
#define helper_stqf helper_stqf_sparc64
#define helper_taddcctv helper_taddcctv_sparc64
#define helper_tsubcctv helper_tsubcctv_sparc64
#define helper_udiv_cc helper_udiv_cc_sparc64
#define sparc_cpu_do_interrupt sparc_cpu_do_interrupt_sparc64
#define sparc_cpu_do_unaligned_access sparc_cpu_do_unaligned_access_sparc64
#define sparc_cpu_get_phys_page_debug sparc_cpu_get_phys_page_debug_sparc64
#define sparc_cpu_handle_mmu_fault sparc_cpu_handle_mmu_fault_sparc64
#define sparc_cpu_register_types sparc_cpu_register_types_sparc64
#define sparc_cpu_unassigned_access sparc_cpu_unassigned_access_sparc64
#define sparc_reg_read sparc_reg_read_sparc64
#define sparc_reg_reset sparc_reg_reset_sparc64
#define sparc_reg_write sparc_reg_write_sparc64
#endif

224
qemu/target-sparc/fop_helper.c
View File

@ -24,43 +24,45 @@
#define QT0 (env->qt0)
#define QT1 (env->qt1)
static void check_ieee_exceptions(CPUSPARCState *env)
target_ulong helper_check_ieee_exceptions(CPUSPARCState *env)
{
target_ulong status;
target_ulong status = get_float_exception_flags(&env->fp_status);
target_ulong fsr = env->fsr;
if (unlikely(status)) {
/* Keep exception flags clear for next time. */
set_float_exception_flags(0, &env->fp_status);
status = get_float_exception_flags(&env->fp_status);
if (status) {
/* Copy IEEE 754 flags into FSR */
if (status & float_flag_invalid) {
env->fsr |= FSR_NVC;
fsr |= FSR_NVC;
}
if (status & float_flag_overflow) {
env->fsr |= FSR_OFC;
fsr |= FSR_OFC;
}
if (status & float_flag_underflow) {
env->fsr |= FSR_UFC;
fsr |= FSR_UFC;
}
if (status & float_flag_divbyzero) {
env->fsr |= FSR_DZC;
fsr |= FSR_DZC;
}
if (status & float_flag_inexact) {
env->fsr |= FSR_NXC;
fsr |= FSR_NXC;
}
if ((env->fsr & FSR_CEXC_MASK) & ((env->fsr & FSR_TEM_MASK) >> 23)) {
/* Unmasked exception, generate a trap */
env->fsr |= FSR_FTT_IEEE_EXCP;
if ((fsr & FSR_CEXC_MASK) & ((fsr & FSR_TEM_MASK) >> 23)) {
/* Unmasked exception, generate a trap. Note that while
the helper is marked as NO_WG, we can get away with
writing to cpu state along the exception path, since
TCG generated code will never see the write. */
env->fsr = fsr | FSR_FTT_IEEE_EXCP;
helper_raise_exception(env, TT_FP_EXCP);
} else {
/* Accumulate exceptions */
env->fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
fsr |= (env->fsr & FSR_CEXC_MASK) << 5;
}
}
}
static inline void clear_float_exceptions(CPUSPARCState *env)
{
set_float_exception_flags(0, &env->fp_status);
return fsr;
}
#define F_HELPER(name, p) void helper_f##name##p(CPUSPARCState *env)
@ -69,26 +71,16 @@ static inline void clear_float_exceptions(CPUSPARCState *env)
float32 helper_f ## name ## s (CPUSPARCState *env, float32 src1, \
float32 src2) \
{ \
float32 ret; \
clear_float_exceptions(env); \
ret = float32_ ## name (src1, src2, &env->fp_status); \
check_ieee_exceptions(env); \
return ret; \
return float32_ ## name (src1, src2, &env->fp_status); \
} \
float64 helper_f ## name ## d (CPUSPARCState * env, float64 src1,\
float64 src2) \
{ \
float64 ret; \
clear_float_exceptions(env); \
ret = float64_ ## name (src1, src2, &env->fp_status); \
check_ieee_exceptions(env); \
return ret; \
return float64_ ## name (src1, src2, &env->fp_status); \
} \
F_HELPER(name, q) \
{ \
clear_float_exceptions(env); \
QT0 = float128_ ## name (QT0, QT1, &env->fp_status); \
check_ieee_exceptions(env); \
}
F_BINOP(add);
@ -99,22 +91,16 @@ F_BINOP(div);
float64 helper_fsmuld(CPUSPARCState *env, float32 src1, float32 src2)
{
float64 ret;
clear_float_exceptions(env);
ret = float64_mul(float32_to_float64(src1, &env->fp_status),
float32_to_float64(src2, &env->fp_status),
&env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_mul(float32_to_float64(src1, &env->fp_status),
float32_to_float64(src2, &env->fp_status),
&env->fp_status);
}
void helper_fdmulq(CPUSPARCState *env, float64 src1, float64 src2)
{
clear_float_exceptions(env);
QT0 = float128_mul(float64_to_float128(src1, &env->fp_status),
float64_to_float128(src2, &env->fp_status),
&env->fp_status);
check_ieee_exceptions(env);
}
float32 helper_fnegs(float32 src)
@ -137,48 +123,32 @@ F_HELPER(neg, q)
/* Integer to float conversion. */
float32 helper_fitos(CPUSPARCState *env, int32_t src)
{
/* Inexact error possible converting int to float. */
float32 ret;
clear_float_exceptions(env);
ret = int32_to_float32(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return int32_to_float32(src, &env->fp_status);
}
float64 helper_fitod(CPUSPARCState *env, int32_t src)
{
/* No possible exceptions converting int to double. */
return int32_to_float64(src, &env->fp_status);
}
void helper_fitoq(CPUSPARCState *env, int32_t src)
{
/* No possible exceptions converting int to long double. */
QT0 = int32_to_float128(src, &env->fp_status);
}
#ifdef TARGET_SPARC64
float32 helper_fxtos(CPUSPARCState *env, int64_t src)
{
float32 ret;
clear_float_exceptions(env);
ret = int64_to_float32(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return int64_to_float32(src, &env->fp_status);
}
float64 helper_fxtod(CPUSPARCState *env, int64_t src)
{
float64 ret;
clear_float_exceptions(env);
ret = int64_to_float64(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return int64_to_float64(src, &env->fp_status);
}
void helper_fxtoq(CPUSPARCState *env, int64_t src)
{
/* No possible exceptions converting long long to long double. */
QT0 = int64_to_float128(src, &env->fp_status);
}
#endif
@ -187,108 +157,64 @@ void helper_fxtoq(CPUSPARCState *env, int64_t src)
/* floating point conversion */
float32 helper_fdtos(CPUSPARCState *env, float64 src)
{
float32 ret;
clear_float_exceptions(env);
ret = float64_to_float32(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_to_float32(src, &env->fp_status);
}
float64 helper_fstod(CPUSPARCState *env, float32 src)
{
float64 ret;
clear_float_exceptions(env);
ret = float32_to_float64(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float32_to_float64(src, &env->fp_status);
}
float32 helper_fqtos(CPUSPARCState *env)
{
float32 ret;
clear_float_exceptions(env);
ret = float128_to_float32(QT1, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float128_to_float32(QT1, &env->fp_status);
}
void helper_fstoq(CPUSPARCState *env, float32 src)
{
clear_float_exceptions(env);
QT0 = float32_to_float128(src, &env->fp_status);
check_ieee_exceptions(env);
}
float64 helper_fqtod(CPUSPARCState *env)
{
float64 ret;
clear_float_exceptions(env);
ret = float128_to_float64(QT1, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float128_to_float64(QT1, &env->fp_status);
}
void helper_fdtoq(CPUSPARCState *env, float64 src)
{
clear_float_exceptions(env);
QT0 = float64_to_float128(src, &env->fp_status);
check_ieee_exceptions(env);
}
/* Float to integer conversion. */
int32_t helper_fstoi(CPUSPARCState *env, float32 src)
{
int32_t ret;
clear_float_exceptions(env);
ret = float32_to_int32_round_to_zero(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float32_to_int32_round_to_zero(src, &env->fp_status);
}
int32_t helper_fdtoi(CPUSPARCState *env, float64 src)
{
int32_t ret;
clear_float_exceptions(env);
ret = float64_to_int32_round_to_zero(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_to_int32_round_to_zero(src, &env->fp_status);
}
int32_t helper_fqtoi(CPUSPARCState *env)
{
int32_t ret;
clear_float_exceptions(env);
ret = float128_to_int32_round_to_zero(QT1, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float128_to_int32_round_to_zero(QT1, &env->fp_status);
}
#ifdef TARGET_SPARC64
int64_t helper_fstox(CPUSPARCState *env, float32 src)
{
int64_t ret;
clear_float_exceptions(env);
ret = float32_to_int64_round_to_zero(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float32_to_int64_round_to_zero(src, &env->fp_status);
}
int64_t helper_fdtox(CPUSPARCState *env, float64 src)
{
int64_t ret;
clear_float_exceptions(env);
ret = float64_to_int64_round_to_zero(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_to_int64_round_to_zero(src, &env->fp_status);
}
int64_t helper_fqtox(CPUSPARCState *env)
{
int64_t ret;
clear_float_exceptions(env);
ret = float128_to_int64_round_to_zero(QT1, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float128_to_int64_round_to_zero(QT1, &env->fp_status);
}
#endif
@ -311,87 +237,79 @@ void helper_fabsq(CPUSPARCState *env)
float32 helper_fsqrts(CPUSPARCState *env, float32 src)
{
float32 ret;
clear_float_exceptions(env);
ret = float32_sqrt(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float32_sqrt(src, &env->fp_status);
}
float64 helper_fsqrtd(CPUSPARCState *env, float64 src)
{
float64 ret;
clear_float_exceptions(env);
ret = float64_sqrt(src, &env->fp_status);
check_ieee_exceptions(env);
return ret;
return float64_sqrt(src, &env->fp_status);
}
void helper_fsqrtq(CPUSPARCState *env)
{
clear_float_exceptions(env);
QT0 = float128_sqrt(QT1, &env->fp_status);
check_ieee_exceptions(env);
}
#define GEN_FCMP(name, size, reg1, reg2, FS, E) \
void glue(helper_, name) (CPUSPARCState *env) \
target_ulong glue(helper_, name) (CPUSPARCState *env) \
{ \
int ret; \
clear_float_exceptions(env); \
target_ulong fsr; \
if (E) { \
ret = glue(size, _compare)(reg1, reg2, &env->fp_status); \
} else { \
ret = glue(size, _compare_quiet)(reg1, reg2, \
&env->fp_status); \
} \
check_ieee_exceptions(env); \
fsr = helper_check_ieee_exceptions(env); \
switch (ret) { \
case float_relation_unordered: \
env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
env->fsr |= FSR_NVA; \
fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
fsr |= FSR_NVA; \
break; \
case float_relation_less: \
env->fsr &= ~(FSR_FCC1) << FS; \
env->fsr |= FSR_FCC0 << FS; \
fsr &= ~(FSR_FCC1) << FS; \
fsr |= FSR_FCC0 << FS; \
break; \
case float_relation_greater: \
env->fsr &= ~(FSR_FCC0) << FS; \
env->fsr |= FSR_FCC1 << FS; \
fsr &= ~(FSR_FCC0) << FS; \
fsr |= FSR_FCC1 << FS; \
break; \
default: \
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
break; \
} \
return fsr; \
}
#define GEN_FCMP_T(name, size, FS, E) \
void glue(helper_, name)(CPUSPARCState *env, size src1, size src2) \
target_ulong glue(helper_, name)(CPUSPARCState *env, size src1, size src2)\
{ \
int ret; \
clear_float_exceptions(env); \
target_ulong fsr; \
if (E) { \
ret = glue(size, _compare)(src1, src2, &env->fp_status); \
} else { \
ret = glue(size, _compare_quiet)(src1, src2, \
&env->fp_status); \
} \
check_ieee_exceptions(env); \
fsr = helper_check_ieee_exceptions(env); \
switch (ret) { \
case float_relation_unordered: \
env->fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
fsr |= (FSR_FCC1 | FSR_FCC0) << FS; \
break; \
case float_relation_less: \
env->fsr &= ~(FSR_FCC1 << FS); \
env->fsr |= FSR_FCC0 << FS; \
fsr &= ~(FSR_FCC1 << FS); \
fsr |= FSR_FCC0 << FS; \
break; \
case float_relation_greater: \
env->fsr &= ~(FSR_FCC0 << FS); \
env->fsr |= FSR_FCC1 << FS; \
fsr &= ~(FSR_FCC0 << FS); \
fsr |= FSR_FCC1 << FS; \
break; \
default: \
env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); \
break; \
} \
return fsr; \
}
GEN_FCMP_T(fcmps, float32, 0, 0);
@ -431,11 +349,11 @@ GEN_FCMP(fcmpeq_fcc3, float128, QT0, QT1, 26, 1);
#undef GEN_FCMP_T
#undef GEN_FCMP
static inline void set_fsr(CPUSPARCState *env)
static void set_fsr(CPUSPARCState *env, target_ulong fsr)
{
int rnd_mode;
switch (env->fsr & FSR_RD_MASK) {
switch (fsr & FSR_RD_MASK) {
case FSR_RD_NEAREST:
rnd_mode = float_round_nearest_even;
break;
@ -453,16 +371,20 @@ static inline void set_fsr(CPUSPARCState *env)
set_float_rounding_mode(rnd_mode, &env->fp_status);
}
void helper_ldfsr(CPUSPARCState *env, uint32_t new_fsr)
target_ulong helper_ldfsr(CPUSPARCState *env, target_ulong old_fsr,
uint32_t new_fsr)
{
env->fsr = (new_fsr & FSR_LDFSR_MASK) | (env->fsr & FSR_LDFSR_OLDMASK);
set_fsr(env);
old_fsr = (new_fsr & FSR_LDFSR_MASK) | (old_fsr & FSR_LDFSR_OLDMASK);
set_fsr(env, old_fsr);
return old_fsr;
}
#ifdef TARGET_SPARC64
void helper_ldxfsr(CPUSPARCState *env, uint64_t new_fsr)
target_ulong helper_ldxfsr(CPUSPARCState *env, target_ulong old_fsr,
uint64_t new_fsr)
{
env->fsr = (new_fsr & FSR_LDXFSR_MASK) | (env->fsr & FSR_LDXFSR_OLDMASK);
set_fsr(env);
old_fsr = (new_fsr & FSR_LDXFSR_MASK) | (old_fsr & FSR_LDXFSR_OLDMASK);
set_fsr(env, old_fsr);
return old_fsr;
}
#endif

112
qemu/target-sparc/helper.h
View File

@ -51,86 +51,88 @@ DEF_HELPER_FLAGS_3(stqf, TCG_CALL_NO_WG, void, env, tl, int)
DEF_HELPER_FLAGS_4(ld_asi, TCG_CALL_NO_WG, i64, env, tl, int, i32)
DEF_HELPER_FLAGS_5(st_asi, TCG_CALL_NO_WG, void, env, tl, i64, int, i32)
#endif
DEF_HELPER_2(ldfsr, void, env, i32)
DEF_HELPER_FLAGS_1(check_ieee_exceptions, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_3(ldfsr, TCG_CALL_NO_RWG, tl, env, tl, i32)
DEF_HELPER_FLAGS_1(fabss, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_2(fsqrts, f32, env, f32)
DEF_HELPER_2(fsqrtd, f64, env, f64)
DEF_HELPER_3(fcmps, void, env, f32, f32)
DEF_HELPER_3(fcmpd, void, env, f64, f64)
DEF_HELPER_3(fcmpes, void, env, f32, f32)
DEF_HELPER_3(fcmped, void, env, f64, f64)
DEF_HELPER_1(fsqrtq, void, env)
DEF_HELPER_1(fcmpq, void, env)
DEF_HELPER_1(fcmpeq, void, env)
DEF_HELPER_FLAGS_2(fsqrts, TCG_CALL_NO_RWG, f32, env, f32)
DEF_HELPER_FLAGS_2(fsqrtd, TCG_CALL_NO_RWG, f64, env, f64)
DEF_HELPER_FLAGS_3(fcmps, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpes, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_1(fsqrtq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_1(fcmpq, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq, TCG_CALL_NO_WG, tl, env)
#ifdef TARGET_SPARC64
DEF_HELPER_2(ldxfsr, void, env, i64)
DEF_HELPER_FLAGS_3(ldxfsr, TCG_CALL_NO_RWG, tl, env, tl, i64)
DEF_HELPER_FLAGS_1(fabsd, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_3(fcmps_fcc1, void, env, f32, f32)
DEF_HELPER_3(fcmps_fcc2, void, env, f32, f32)
DEF_HELPER_3(fcmps_fcc3, void, env, f32, f32)
DEF_HELPER_3(fcmpd_fcc1, void, env, f64, f64)
DEF_HELPER_3(fcmpd_fcc2, void, env, f64, f64)
DEF_HELPER_3(fcmpd_fcc3, void, env, f64, f64)
DEF_HELPER_3(fcmpes_fcc1, void, env, f32, f32)
DEF_HELPER_3(fcmpes_fcc2, void, env, f32, f32)
DEF_HELPER_3(fcmpes_fcc3, void, env, f32, f32)
DEF_HELPER_3(fcmped_fcc1, void, env, f64, f64)
DEF_HELPER_3(fcmped_fcc2, void, env, f64, f64)
DEF_HELPER_3(fcmped_fcc3, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmps_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmps_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpd_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpd_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpd_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmpes_fcc1, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpes_fcc2, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmpes_fcc3, TCG_CALL_NO_WG, tl, env, f32, f32)
DEF_HELPER_FLAGS_3(fcmped_fcc1, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped_fcc2, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_3(fcmped_fcc3, TCG_CALL_NO_WG, tl, env, f64, f64)
DEF_HELPER_FLAGS_1(fabsq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_1(fcmpq_fcc1, void, env)
DEF_HELPER_1(fcmpq_fcc2, void, env)
DEF_HELPER_1(fcmpq_fcc3, void, env)
DEF_HELPER_1(fcmpeq_fcc1, void, env)
DEF_HELPER_1(fcmpeq_fcc2, void, env)
DEF_HELPER_1(fcmpeq_fcc3, void, env)
DEF_HELPER_FLAGS_1(fcmpq_fcc1, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpq_fcc2, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpq_fcc3, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq_fcc1, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq_fcc2, TCG_CALL_NO_WG, tl, env)
DEF_HELPER_FLAGS_1(fcmpeq_fcc3, TCG_CALL_NO_WG, tl, env)
#endif
DEF_HELPER_2(raise_exception, noreturn, env, int)
#define F_HELPER_0_1(name) DEF_HELPER_1(f ## name, void, env)
#define F_HELPER_0_1(name) \
DEF_HELPER_FLAGS_1(f ## name, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_3(faddd, f64, env, f64, f64)
DEF_HELPER_3(fsubd, f64, env, f64, f64)
DEF_HELPER_3(fmuld, f64, env, f64, f64)
DEF_HELPER_3(fdivd, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_RWG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fsubd, TCG_CALL_NO_RWG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fmuld, TCG_CALL_NO_RWG, f64, env, f64, f64)
DEF_HELPER_FLAGS_3(fdivd, TCG_CALL_NO_RWG, f64, env, f64, f64)
F_HELPER_0_1(addq)
F_HELPER_0_1(subq)
F_HELPER_0_1(mulq)
F_HELPER_0_1(divq)
DEF_HELPER_3(fadds, f32, env, f32, f32)
DEF_HELPER_3(fsubs, f32, env, f32, f32)
DEF_HELPER_3(fmuls, f32, env, f32, f32)
DEF_HELPER_3(fdivs, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fadds, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fsubs, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fmuls, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_FLAGS_3(fdivs, TCG_CALL_NO_RWG, f32, env, f32, f32)
DEF_HELPER_3(fsmuld, f64, env, f32, f32)
DEF_HELPER_3(fdmulq, void, env, f64, f64)
DEF_HELPER_FLAGS_3(fsmuld, TCG_CALL_NO_RWG, f64, env, f32, f32)
DEF_HELPER_FLAGS_3(fdmulq, TCG_CALL_NO_RWG, void, env, f64, f64)
DEF_HELPER_FLAGS_1(fnegs, TCG_CALL_NO_RWG_SE, f32, f32)
DEF_HELPER_FLAGS_2(fitod, TCG_CALL_NO_RWG_SE, f64, env, s32)
DEF_HELPER_FLAGS_2(fitoq, TCG_CALL_NO_RWG, void, env, s32)
DEF_HELPER_2(fitos, f32, env, s32)
DEF_HELPER_FLAGS_2(fitos, TCG_CALL_NO_RWG, f32, env, s32)
#ifdef TARGET_SPARC64
DEF_HELPER_FLAGS_1(fnegd, TCG_CALL_NO_RWG_SE, f64, f64)
DEF_HELPER_FLAGS_1(fnegq, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_2(fxtos, f32, env, s64)
DEF_HELPER_2(fxtod, f64, env, s64)
DEF_HELPER_FLAGS_2(fxtos, TCG_CALL_NO_RWG, f32, env, s64)
DEF_HELPER_FLAGS_2(fxtod, TCG_CALL_NO_RWG, f64, env, s64)
DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64)
#endif
DEF_HELPER_2(fdtos, f32, env, f64)
DEF_HELPER_2(fstod, f64, env, f32)
DEF_HELPER_1(fqtos, f32, env)
DEF_HELPER_2(fstoq, void, env, f32)
DEF_HELPER_1(fqtod, f64, env)
DEF_HELPER_2(fdtoq, void, env, f64)
DEF_HELPER_2(fstoi, s32, env, f32)
DEF_HELPER_2(fdtoi, s32, env, f64)
DEF_HELPER_1(fqtoi, s32, env)
DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64)
DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32)
DEF_HELPER_FLAGS_1(fqtos, TCG_CALL_NO_RWG, f32, env)
DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32)
DEF_HELPER_FLAGS_1(fqtod, TCG_CALL_NO_RWG, f64, env)
DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64)
DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32)
DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64)
DEF_HELPER_FLAGS_1(fqtoi, TCG_CALL_NO_RWG, s32, env)
#ifdef TARGET_SPARC64
DEF_HELPER_2(fstox, s64, env, f32)
DEF_HELPER_2(fdtox, s64, env, f64)
DEF_HELPER_1(fqtox, s64, env)
DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32)
DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64)
DEF_HELPER_FLAGS_1(fqtox, TCG_CALL_NO_RWG, s64, env)
DEF_HELPER_FLAGS_2(fpmerge, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(fmul8x16, TCG_CALL_NO_RWG_SE, i64, i64, i64)

94
qemu/target-sparc/translate.c
View File

@ -1608,16 +1608,20 @@ static inline void gen_op_fcmps(DisasContext *dc, int fccno, TCGv_i32 r_rs1, TCG
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
switch (fccno) {
case 0:
gen_helper_fcmps(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmps(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 1:
gen_helper_fcmps_fcc1(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmps_fcc1(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 2:
gen_helper_fcmps_fcc2(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmps_fcc2(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 3:
gen_helper_fcmps_fcc3(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmps_fcc3(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
}
}
@ -1627,16 +1631,20 @@ static inline void gen_op_fcmpd(DisasContext *dc, int fccno, TCGv_i64 r_rs1, TCG
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
switch (fccno) {
case 0:
gen_helper_fcmpd(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpd(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 1:
gen_helper_fcmpd_fcc1(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpd_fcc1(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 2:
gen_helper_fcmpd_fcc2(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpd_fcc2(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 3:
gen_helper_fcmpd_fcc3(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpd_fcc3(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
}
}
@ -1646,16 +1654,16 @@ static inline void gen_op_fcmpq(DisasContext *dc, int fccno)
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
switch (fccno) {
case 0:
gen_helper_fcmpq(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpq(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
break;
case 1:
gen_helper_fcmpq_fcc1(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpq_fcc1(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
break;
case 2:
gen_helper_fcmpq_fcc2(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpq_fcc2(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
break;
case 3:
gen_helper_fcmpq_fcc3(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpq_fcc3(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
break;
}
}
@ -1665,16 +1673,20 @@ static inline void gen_op_fcmpes(DisasContext *dc, int fccno, TCGv_i32 r_rs1, TC
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
switch (fccno) {
case 0:
gen_helper_fcmpes(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpes(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 1:
gen_helper_fcmpes_fcc1(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpes_fcc1(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 2:
gen_helper_fcmpes_fcc2(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpes_fcc2(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 3:
gen_helper_fcmpes_fcc3(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpes_fcc3(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
}
}
@ -1684,16 +1696,20 @@ static inline void gen_op_fcmped(DisasContext *dc, int fccno, TCGv_i64 r_rs1, TC
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
switch (fccno) {
case 0:
gen_helper_fcmped(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmped(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 1:
gen_helper_fcmped_fcc1(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmped_fcc1(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 2:
gen_helper_fcmped_fcc2(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmped_fcc2(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
case 3:
gen_helper_fcmped_fcc3(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmped_fcc3(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
break;
}
}
@ -1703,16 +1719,16 @@ static inline void gen_op_fcmpeq(DisasContext *dc, int fccno)
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
switch (fccno) {
case 0:
gen_helper_fcmpeq(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpeq(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
break;
case 1:
gen_helper_fcmpeq_fcc1(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpeq_fcc1(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
break;
case 2:
gen_helper_fcmpeq_fcc2(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpeq_fcc2(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
break;
case 3:
gen_helper_fcmpeq_fcc3(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpeq_fcc3(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
break;
}
}
@ -1722,37 +1738,39 @@ static inline void gen_op_fcmpeq(DisasContext *dc, int fccno)
static inline void gen_op_fcmps(DisasContext *dc, int fccno, TCGv r_rs1, TCGv r_rs2)
{
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
gen_helper_fcmps(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmps(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env, r_rs1, r_rs2);
}
static inline void gen_op_fcmpd(DisasContext *dc, int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
{
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
gen_helper_fcmpd(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpd(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
}
static inline void gen_op_fcmpq(DisasContext *dc, int fccno)
{
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
gen_helper_fcmpq(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpq(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
}
static inline void gen_op_fcmpes(DisasContext *dc, int fccno, TCGv r_rs1, TCGv r_rs2)
{
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
gen_helper_fcmpes(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmpes(tcg_ctx, tcg_ctx->cpu_fsr,
tcg_ctx->cpu_env, r_rs1, r_rs2);
}
static inline void gen_op_fcmped(DisasContext *dc, int fccno, TCGv_i64 r_rs1, TCGv_i64 r_rs2)
{
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
gen_helper_fcmped(tcg_ctx, tcg_ctx->cpu_env, r_rs1, r_rs2);
gen_helper_fcmped(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env, r_rs1, r_rs2);
}
static inline void gen_op_fcmpeq(DisasContext *dc, int fccno)
{
TCGContext *tcg_ctx = dc->uc->tcg_ctx;
gen_helper_fcmpeq(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_fcmpeq(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
}
#endif
@ -1792,6 +1810,7 @@ static inline void gen_fop_FF(DisasContext *dc, int rd, int rs,
dst = gen_dest_fpr_F(dc);
gen(tcg_ctx, dst, tcg_ctx->cpu_env, src);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_store_fpr_F(dc, rd, dst);
}
@ -1821,6 +1840,7 @@ static inline void gen_fop_FFF(DisasContext *dc, int rd, int rs1, int rs2,
dst = gen_dest_fpr_F(dc);
gen(tcg_ctx, dst, tcg_ctx->cpu_env, src1, src2);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_store_fpr_F(dc, rd, dst);
}
@ -1852,6 +1872,7 @@ static inline void gen_fop_DD(DisasContext *dc, int rd, int rs,
dst = gen_dest_fpr_D(dc, rd);
gen(tcg_ctx, dst, tcg_ctx->cpu_env, src);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_store_fpr_D(dc, rd, dst);
}
@ -1883,6 +1904,7 @@ static inline void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
dst = gen_dest_fpr_D(dc, rd);
gen(tcg_ctx, dst, tcg_ctx->cpu_env, src1, src2);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_store_fpr_D(dc, rd, dst);
}
@ -1942,6 +1964,7 @@ static inline void gen_fop_QQ(DisasContext *dc, int rd, int rs,
gen_op_load_fpr_QT1(dc, QFPREG(rs));
gen(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_op_store_QT0_fpr(dc, QFPREG(rd));
gen_update_fprs_dirty(dc, QFPREG(rd));
@ -1969,6 +1992,7 @@ static inline void gen_fop_QQQ(DisasContext *dc, int rd, int rs1, int rs2,
gen_op_load_fpr_QT1(dc, QFPREG(rs2));
gen(tcg_ctx, tcg_ctx->cpu_env);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_op_store_QT0_fpr(dc, QFPREG(rd));
gen_update_fprs_dirty(dc, QFPREG(rd));
@ -1986,6 +2010,7 @@ static inline void gen_fop_DFF(DisasContext *dc, int rd, int rs1, int rs2,
dst = gen_dest_fpr_D(dc, rd);
gen(tcg_ctx, dst, tcg_ctx->cpu_env, src1, src2);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_store_fpr_D(dc, rd, dst);
}
@ -2000,6 +2025,7 @@ static inline void gen_fop_QDD(DisasContext *dc, int rd, int rs1, int rs2,
src2 = gen_load_fpr_D(dc, rs2);
gen(tcg_ctx, tcg_ctx->cpu_env, src1, src2);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_op_store_QT0_fpr(dc, QFPREG(rd));
gen_update_fprs_dirty(dc, QFPREG(rd));
@ -2017,6 +2043,7 @@ static inline void gen_fop_DF(DisasContext *dc, int rd, int rs,
dst = gen_dest_fpr_D(dc, rd);
gen(tcg_ctx, dst, tcg_ctx->cpu_env, src);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_store_fpr_D(dc, rd, dst);
}
@ -2048,6 +2075,7 @@ static inline void gen_fop_FD(DisasContext *dc, int rd, int rs,
dst = gen_dest_fpr_F(dc);
gen(tcg_ctx, dst, tcg_ctx->cpu_env, src);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_store_fpr_F(dc, rd, dst);
}
@ -2062,6 +2090,7 @@ static inline void gen_fop_FQ(DisasContext *dc, int rd, int rs,
dst = gen_dest_fpr_F(dc);
gen(tcg_ctx, dst, tcg_ctx->cpu_env);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_store_fpr_F(dc, rd, dst);
}
@ -2076,6 +2105,7 @@ static inline void gen_fop_DQ(DisasContext *dc, int rd, int rs,
dst = gen_dest_fpr_D(dc, rd);
gen(tcg_ctx, dst, tcg_ctx->cpu_env);
gen_helper_check_ieee_exceptions(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env);
gen_store_fpr_D(dc, rd, dst);
}
@ -5440,7 +5470,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
if (rd == 1) {
TCGv_i64 t64 = tcg_temp_new_i64(tcg_ctx);
tcg_gen_qemu_ld64(dc->uc, t64, cpu_addr, dc->mem_idx);
gen_helper_ldxfsr(tcg_ctx, tcg_ctx->cpu_env, t64);
gen_helper_ldxfsr(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env, tcg_ctx->cpu_fsr, t64);
tcg_temp_free_i64(tcg_ctx, t64);
break;
}
@ -5449,7 +5479,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn, bool hook_ins
t0 = get_temp_tl(dc);
tcg_gen_qemu_ld32u(dc->uc, t0, cpu_addr, dc->mem_idx);
tcg_gen_trunc_tl_i32(tcg_ctx, cpu_dst_32, t0);
gen_helper_ldfsr(tcg_ctx, tcg_ctx->cpu_env, cpu_dst_32);
gen_helper_ldfsr(tcg_ctx, tcg_ctx->cpu_fsr, tcg_ctx->cpu_env, tcg_ctx->cpu_fsr, cpu_dst_32);
break;
case 0x22: /* ldqf, load quad fpreg */
{