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target/riscv: vector widening floating-point multiply

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Backports f7c7b7cd293ca6f14f23cc2c14d6d23fc47a604d
This commit is contained in:
LIU Zhiwei 2021-03-07 11:32:17 -05:00 committed by Lioncash
parent 5e4b142c31
commit 14cbabde4f
7 changed files with 45 additions and 0 deletions
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4
qemu/header_gen.py
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@ -7023,6 +7023,10 @@ riscv_symbols = (
'helper_vfrdiv_vf_h',
'helper_vfrdiv_vf_w',
'helper_vfrdiv_vf_d',
'helper_vfwmul_vv_h',
'helper_vfwmul_vv_w',
'helper_vfwmul_vf_h',
'helper_vfwmul_vf_w',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

4
qemu/riscv32.h
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@ -4459,6 +4459,10 @@
#define helper_vfrdiv_vf_h helper_vfrdiv_vf_h_riscv32
#define helper_vfrdiv_vf_w helper_vfrdiv_vf_w_riscv32
#define helper_vfrdiv_vf_d helper_vfrdiv_vf_d_riscv32
#define helper_vfwmul_vv_h helper_vfwmul_vv_h_riscv32
#define helper_vfwmul_vv_w helper_vfwmul_vv_w_riscv32
#define helper_vfwmul_vf_h helper_vfwmul_vf_h_riscv32
#define helper_vfwmul_vf_w helper_vfwmul_vf_w_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

4
qemu/riscv64.h
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@ -4459,6 +4459,10 @@
#define helper_vfrdiv_vf_h helper_vfrdiv_vf_h_riscv64
#define helper_vfrdiv_vf_w helper_vfrdiv_vf_w_riscv64
#define helper_vfrdiv_vf_d helper_vfrdiv_vf_d_riscv64
#define helper_vfwmul_vv_h helper_vfwmul_vv_h_riscv64
#define helper_vfwmul_vv_w helper_vfwmul_vv_w_riscv64
#define helper_vfwmul_vf_h helper_vfwmul_vf_h_riscv64
#define helper_vfwmul_vf_w helper_vfwmul_vf_w_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

5
qemu/target/riscv/helper.h
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@ -855,3 +855,8 @@ DEF_HELPER_6(vfdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrdiv_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrdiv_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfrdiv_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfwmul_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfwmul_vf_w, void, ptr, ptr, i64, ptr, env, i32)

2
qemu/target/riscv/insn32.decode
View File

@ -463,6 +463,8 @@ vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm
vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

4
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View File

@ -2089,3 +2089,7 @@ GEN_OPFVV_TRANS(vfdiv_vv, opfvv_check)
GEN_OPFVF_TRANS(vfmul_vf, opfvf_check)
GEN_OPFVF_TRANS(vfdiv_vf, opfvf_check)
GEN_OPFVF_TRANS(vfrdiv_vf, opfvf_check)
/* Vector Widening Floating-Point Multiply */
GEN_OPFVV_WIDEN_TRANS(vfwmul_vv, opfvv_widen_check)
GEN_OPFVF_WIDEN_TRANS(vfwmul_vf)

22
qemu/target/riscv/vector_helper.c
View File

@ -3411,3 +3411,25 @@ RVVCALL(OPFVF2, vfrdiv_vf_d, OP_UUU_D, H8, H8, float64_rdiv)
GEN_VEXT_VF(vfrdiv_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfrdiv_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfrdiv_vf_d, 8, 8, clearq)
/* Vector Widening Floating-Point Multiply */
static uint32_t vfwmul16(uint16_t a, uint16_t b, float_status *s)
{
return float32_mul(float16_to_float32(a, true, s),
float16_to_float32(b, true, s), s);
}
static uint64_t vfwmul32(uint32_t a, uint32_t b, float_status *s)
{
return float64_mul(float32_to_float64(a, s),
float32_to_float64(b, s), s);
}
RVVCALL(OPFVV2, vfwmul_vv_h, WOP_UUU_H, H4, H2, H2, vfwmul16)
RVVCALL(OPFVV2, vfwmul_vv_w, WOP_UUU_W, H8, H4, H4, vfwmul32)
GEN_VEXT_VV_ENV(vfwmul_vv_h, 2, 4, clearl)
GEN_VEXT_VV_ENV(vfwmul_vv_w, 4, 8, clearq)
RVVCALL(OPFVF2, vfwmul_vf_h, WOP_UUU_H, H4, H2, vfwmul16)
RVVCALL(OPFVF2, vfwmul_vf_w, WOP_UUU_W, H8, H4, vfwmul32)
GEN_VEXT_VF(vfwmul_vf_h, 2, 4, clearl)
GEN_VEXT_VF(vfwmul_vf_w, 4, 8, clearq)