diff --git a/qemu/target/mips/translate_init.c b/qemu/target/mips/translate_init.c
index 7bbcea8e..b44db3d7 100644
--- a/qemu/target/mips/translate_init.c
+++ b/qemu/target/mips/translate_init.c
@@ -584,12 +584,14 @@ static const mips_def_t mips_defs[] =
                        (1 << CP0C1_PC) | (1 << CP0C1_FP),
         MIPS_CONFIG2,
         MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) |
-                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) |
-                       (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt),
+                       (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_SC) |
+                       (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) |
+                       (1 << CP0C3_VInt),
         MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |
                        (0x1c << CP0C4_KScrExist),
         0,
-        MIPS_CONFIG5 | (1 << CP0C5_MVH) | (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
+        MIPS_CONFIG5 | (1 << CP0C5_EVA) | (1 << CP0C5_MVH) |
+                       (1 << CP0C5_LLB) | (1 << CP0C5_MRP),
         (1 << CP0C5_K) | (1 << CP0C5_CV) |
                          (1 << CP0C5_MSAEn) | (1 << CP0C5_UFE) |
                          (1 << CP0C5_FRE) | (1 << CP0C5_UFR),
@@ -613,7 +615,7 @@ static const mips_def_t mips_defs[] =
         0,0, 0,0, 0,0, 0,0, 0,0,
         (1U << CP0PG_RIE) | (1 << CP0PG_XIE) | (1 << CP0PG_ELPA) | (1 << CP0PG_IEC),
         0,
-        0,
+        (1 << CP0EBase_WG),
         CPU_MIPS32R5 | ASE_MSA,
         MMU_TYPE_R4000,
     },