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target/arm: Remove ARM_CP_64BIT from ZCR_EL registers

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Because they are ARM_CP_STATE_AA64, ARM_CP_64BIT is implied.

Backports commit 5d1e699988cdb1494ab4ac9a2b67d4c539143654 from qemu
This commit is contained in:
Richard Henderson 2018-03-08 09:03:46 -05:00 committed by Lioncash
parent c88064b52c
commit 1bff556dbc
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 4 deletions
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8
qemu/target/arm/helper.c
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@ -3836,25 +3836,25 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
static const ARMCPRegInfo zcr_el1_reginfo = {
"ZCR_EL1", 0,1,2, 3,0,0, ARM_CP_STATE_AA64, ARM_CP_64BIT,
"ZCR_EL1", 0,1,2, 3,0,0, ARM_CP_STATE_AA64, 0,
PL1_RW, 0, NULL, 0, offsetof(CPUARMState, vfp.zcr_el[1]), {0, 0},
zcr_access, NULL, zcr_write, NULL, raw_write
};
static const ARMCPRegInfo zcr_el2_reginfo = {
"ZCR_EL2", 0,1,2, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_64BIT,
"ZCR_EL2", 0,1,2, 3,4,0, ARM_CP_STATE_AA64, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, vfp.zcr_el[2]), {0, 0},
zcr_access, NULL, zcr_write, NULL, raw_write
};
static const ARMCPRegInfo zcr_no_el2_reginfo = {
"ZCR_EL2", 0,1,2, 3,4,0, ARM_CP_STATE_AA64, ARM_CP_64BIT,
"ZCR_EL2", 0,1,2, 3,4,0, ARM_CP_STATE_AA64, 0,
PL2_RW, 0, NULL, 0, 0, {0, 0},
NULL, arm_cp_read_zero, arm_cp_write_ignore
};
static const ARMCPRegInfo zcr_el3_reginfo = {
"ZCR_EL3", 0,1,2, 3,6,0, ARM_CP_STATE_AA64, ARM_CP_64BIT,
"ZCR_EL3", 0,1,2, 3,6,0, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, vfp.zcr_el[3]), {0, 0},
zcr_access, NULL, zcr_write, NULL, raw_write
};