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target-arm: make DFSR banked

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When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
DFSR has a secure and a non-secure instance.

Backports commit 4a7e2d7315bd2ce28e49ccd0bde73eabdfd7437b from qemu
This commit is contained in:
Fabian Aggeler 2018-02-12 09:10:35 -05:00 committed by Lioncash
parent 192c5c665a
commit 27ba8b30c5
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
2 changed files with 13 additions and 4 deletions
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8
qemu/target-arm/cpu.h
View File

@ -253,7 +253,15 @@ typedef struct CPUARMState {
uint64_t ifsr32_el2;
};
};
union {
struct {
uint64_t _unused_dfsr;
uint64_t dfsr_ns;
uint64_t hsr;
uint64_t dfsr_s;
};
uint64_t esr_el[4];
};
uint32_t c6_region[8]; /* MPU base/size registers. */
uint64_t far_el[4]; /* Fault address registers. */
uint64_t par_el1; /* Translation result. */

7
qemu/target-arm/helper.c
View File

@ -1408,7 +1408,8 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
{ "DFSR", 15,5,0, 0,0,0, 0,
ARM_CP_NO_MIGRATE, PL1_RW, 0, NULL, 0, offsetoflow32(CPUARMState, cp15.esr_el[1]), {0, 0},
ARM_CP_NO_MIGRATE, PL1_RW, 0, NULL, 0, 0,
{ offsetoflow32(CPUARMState, cp15.dfsr_s), offsetoflow32(CPUARMState, cp15.dfsr_ns) },
NULL,NULL,NULL,NULL,NULL, arm_cp_reset_ignore, },
{ "IFSR", 15,5,0, 0,0,1, 0,
0, PL1_RW, 0, NULL, 0, 0,
@ -3837,11 +3838,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
offset = 4;
break;
case EXCP_DATA_ABORT:
env->cp15.esr_el[1] = env->exception.fsr;
A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
env->exception.vaddress);
qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
(uint32_t)env->cp15.esr_el[1],
env->exception.fsr,
(uint32_t)env->exception.vaddress);
new_mode = ARM_CPU_MODE_ABT;
addr = 0x10;