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target/arm: Implement HCR.VI and VF

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The HCR_EL2 VI and VF bits are supposed to track whether there is
a pending virtual IRQ or virtual FIQ. For QEMU we store the
pending VIRQ/VFIQ status in cs->interrupt_request, so this means:
* if the register is read we must get these bit values from
cs->interrupt_request
* if the register is written then we must write the bit
values back into cs->interrupt_request

Backports commit 8a0fc3a29fc2315325400c738f807d0d4ae0ab7f from qemu
This commit is contained in:
Peter Maydell 2018-11-10 09:23:17 -05:00 committed by Lioncash
parent 0f0befc90a
commit 28fcb58c69
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 44 additions and 5 deletions
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49
qemu/target/arm/helper.c
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@ -3485,6 +3485,7 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = {
static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = ENV_GET_CPU(env);
uint64_t valid_mask = HCR_MASK;
if (arm_feature(env, ARM_FEATURE_EL3)) {
@ -3503,6 +3504,29 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
/* Clear RES0 bits. */
value &= valid_mask;
/*
* VI and VF are kept in cs->interrupt_request. Modifying that
* requires that we have the iothread lock, which is done by
* marking the reginfo structs as ARM_CP_IO.
* Note that if a write to HCR pends a VIRQ or VFIQ it is never
* possible for it to be taken immediately, because VIRQ and
* VFIQ are masked unless running at EL0 or EL1, and HCR
* can only be written at EL2.
*/
// Unicorn: Commented out
//g_assert(qemu_mutex_iothread_locked());
if (value & HCR_VI) {
cs->interrupt_request |= CPU_INTERRUPT_VIRQ;
} else {
cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
}
if (value & HCR_VF) {
cs->interrupt_request |= CPU_INTERRUPT_VFIQ;
} else {
cs->interrupt_request &= ~CPU_INTERRUPT_VFIQ;
}
value &= ~(HCR_VI | HCR_VF);
/* These bits change the MMU setup:
* HCR_VM enables stage 2 translation
* HCR_PTW forbids certain page-table setups
@ -3530,13 +3554,28 @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
hcr_write(env, NULL, value);
}
static uint64_t hcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
/* The VI and VF bits live in cs->interrupt_request */
uint64_t ret = env->cp15.hcr_el2 & ~(HCR_VI | HCR_VF);
CPUState *cs = ENV_GET_CPU(env);
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
ret |= HCR_VI;
}
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
ret |= HCR_VF;
}
return ret;
}
static const ARMCPRegInfo el2_cp_reginfo[] = {
{ "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_AA64,
0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.hcr_el2), {0, 0},
NULL, NULL, hcr_write },
ARM_CP_IO, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.hcr_el2), {0, 0},
NULL, hcr_read, hcr_write },
{ "HCR", 15,1,1, 0,4,0, ARM_CP_STATE_AA32,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.hcr_el2),
{0, 0}, NULL, NULL, hcr_writelow },
ARM_CP_ALIAS | ARM_CP_IO, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.hcr_el2),
{0, 0}, NULL, hcr_read, hcr_writelow },
{ "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) },
{ "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_BOTH, 0,
@ -3700,7 +3739,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
static const ARMCPRegInfo el2_v8_cp_reginfo[] = {
{ "HCR2", 15,1,1, 0,4,4, ARM_CP_STATE_AA32,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.hcr_el2),
ARM_CP_ALIAS | ARM_CP_IO, PL2_RW, 0, NULL, 0, offsetofhigh32(CPUARMState, cp15.hcr_el2),
{0, 0}, NULL, NULL, hcr_writehigh },
REGINFO_SENTINEL
};