From 2edba8fcfebea85bdf22598c13ecb4e91ba76a81 Mon Sep 17 00:00:00 2001 From: Zong Li Date: Mon, 8 Mar 2021 12:43:33 -0500 Subject: [PATCH] target/riscv: Fix the translation of physical address The real physical address should add the 12 bits page offset. It also causes the PMP wrong checking due to the minimum granularity of PMP is 4 byte, but we always get the physical address which is 4KB alignment, that means, we always use the start address of the page to check PMP for all addresses which in the same page. Backports 9ef82119b10d996cef63af679af5c1a7a85e6c19 --- qemu/target/riscv/cpu_helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qemu/target/riscv/cpu_helper.c b/qemu/target/riscv/cpu_helper.c index 3e35b595..d0dd9da8 100644 --- a/qemu/target/riscv/cpu_helper.c +++ b/qemu/target/riscv/cpu_helper.c @@ -537,7 +537,8 @@ restart: /* for superpage mappings, make a fake leaf PTE for the TLB's benefit. */ target_ulong vpn = addr >> PGSHIFT; - *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; + *physical = ((ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT) | + (addr & ~TARGET_PAGE_MASK); /* set permissions on the TLB entry */ if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { @@ -624,7 +625,7 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) } } - return phys_addr; + return phys_addr & TARGET_PAGE_MASK; } void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,