From 3173269986e4fbf09f3b86176f604edcae1dcdb8 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sun, 11 Feb 2018 01:35:31 -0500 Subject: [PATCH] target-arm: Eliminate unnecessary zero-extend in disas_bitfield For !SF, this initial ext32u can't be optimized away by the current TCG code generator. (It would require backward bit liveness propagation.) Backports commit d3a77b42decd0cbfa62a5526e67d1d6d380c83a9 from qemu --- qemu/target-arm/translate-a64.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c index 30ad5b4c..24ba7320 100644 --- a/qemu/target-arm/translate-a64.c +++ b/qemu/target-arm/translate-a64.c @@ -3009,7 +3009,12 @@ static void disas_bitfield(DisasContext *s, uint32_t insn) } tcg_rd = cpu_reg(s, rd); - tcg_tmp = read_cpu_reg(s, rn, sf); + + /* Suppress the zero-extend for !sf. Since RI and SI are constrained + to be smaller than bitsize, we'll never reference data outside the + low 32-bits anyway. */ + tcg_tmp = read_cpu_reg(s, rn, 1); + /* Recognize the common aliases. */ if (opc == 0) { /* SBFM */