From 349227bb05fb2c153c1e034f5162d0cf6e3218c5 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 2 Mar 2018 19:13:34 -0500 Subject: [PATCH] arm: Don't let no-MPU PMSA cores write to SCTLR.M If the CPU is a PMSA config with no MPU implemented, then the SCTLR.M bit should be RAZ/WI, so that the guest can never turn on the non-existent MPU. Backports commit 06312febfb2d35367006ef23608ddd6a131214d4 from qemu --- qemu/target/arm/helper.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index ad5a7df6..eee3adb6 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -2984,6 +2984,11 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, return; } + if (arm_feature(env, ARM_FEATURE_PMSA) && !cpu->has_mpu) { + /* M bit is RAZ/WI for PMSA with no MPU implemented */ + value &= ~SCTLR_M; + } + raw_write(env, ri, value); /* ??? Lots of these bits are not implemented. */ /* This may enable/disable the MMU, so do a TLB flush. */