From 382dcb2deb842b3b7db06d57ebee575d3c2bcff0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Sat, 3 Mar 2018 23:21:26 -0500 Subject: [PATCH] target/sparc: optimize gen_op_mulscc() using deposit op Backports commit 08d64e0db02e826b063d2b0d8b84f1cb1f7306c9 from qemu --- qemu/target/sparc/translate.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/qemu/target/sparc/translate.c b/qemu/target/sparc/translate.c index 082af557..a35fc2ca 100644 --- a/qemu/target/sparc/translate.c +++ b/qemu/target/sparc/translate.c @@ -676,11 +676,8 @@ static inline void gen_op_mulscc(DisasContext *dc, TCGv dst, TCGv src1, TCGv src // b2 = T0 & 1; // env->y = (b2 << 31) | (env->y >> 1); - tcg_gen_andi_tl(tcg_ctx, r_temp, tcg_ctx->cpu_cc_src, 0x1); - tcg_gen_shli_tl(tcg_ctx, r_temp, r_temp, 31); tcg_gen_extract_tl(tcg_ctx, t0, tcg_ctx->cpu_y, 1, 31); - tcg_gen_or_tl(tcg_ctx, t0, t0, r_temp); - tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_y, t0, 0xffffffff); + tcg_gen_deposit_tl(tcg_ctx, tcg_ctx->cpu_y, t0, tcg_ctx->cpu_cc_src, 31, 1); // b1 = N ^ V; gen_mov_reg_N(dc, t0, tcg_ctx->cpu_psr);