From 436e092e36045ea9e2e1e0635e2906743540c72e Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Fri, 5 Mar 2021 09:08:53 -0500 Subject: [PATCH] target/riscv: vector widening integer multiply instructions Backports 97b1cba39967251ab78b9d52fd9a4c62bb42d428 --- qemu/header_gen.py | 18 +++++++ qemu/riscv32.h | 18 +++++++ qemu/riscv64.h | 18 +++++++ qemu/target/riscv/helper.h | 19 ++++++++ qemu/target/riscv/insn32.decode | 6 +++ qemu/target/riscv/insn_trans/trans_rvv.inc.c | 8 +++ qemu/target/riscv/vector_helper.c | 51 ++++++++++++++++++++ 7 files changed, 138 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 41bcf45f..87f470d9 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -6755,6 +6755,24 @@ riscv_symbols = ( 'helper_vrem_vx_h', 'helper_vrem_vx_w', 'helper_vrem_vx_d', + 'helpet_vwmul_vv_b', + 'helpet_vwmul_vv_h', + 'helpet_vwmul_vv_w', + 'helpet_vwmulu_vv_b', + 'helpet_vwmulu_vv_h', + 'helpet_vwmulu_vv_w', + 'helpet_vwmulsu_vv_b', + 'helpet_vwmulsu_vv_h', + 'helpet_vwmulsu_vv_w', + 'helpet_vwmul_vx_b', + 'helpet_vwmul_vx_h', + 'helpet_vwmul_vx_w', + 'helpet_vwmulu_vx_b', + 'helpet_vwmulu_vx_h', + 'helpet_vwmulu_vx_w', + 'helpet_vwmulsu_vx_b', + 'helpet_vwmulsu_vx_h', + 'helpet_vwmulsu_vx_w', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index c428702b..4c3d8539 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4191,6 +4191,24 @@ #define helper_vrem_vx_h helper_vrem_vx_h_riscv32 #define helper_vrem_vx_w helper_vrem_vx_w_riscv32 #define helper_vrem_vx_d helper_vrem_vx_d_riscv32 +#define helpet_vwmul_vv_b helpet_vwmul_vv_b_riscv32 +#define helpet_vwmul_vv_h helpet_vwmul_vv_h_riscv32 +#define helpet_vwmul_vv_w helpet_vwmul_vv_w_riscv32 +#define helpet_vwmulu_vv_b helpet_vwmulu_vv_b_riscv32 +#define helpet_vwmulu_vv_h helpet_vwmulu_vv_h_riscv32 +#define helpet_vwmulu_vv_w helpet_vwmulu_vv_w_riscv32 +#define helpet_vwmulsu_vv_b helpet_vwmulsu_vv_b_riscv32 +#define helpet_vwmulsu_vv_h helpet_vwmulsu_vv_h_riscv32 +#define helpet_vwmulsu_vv_w helpet_vwmulsu_vv_w_riscv32 +#define helpet_vwmul_vx_b helpet_vwmul_vx_b_riscv32 +#define helpet_vwmul_vx_h helpet_vwmul_vx_h_riscv32 +#define helpet_vwmul_vx_w helpet_vwmul_vx_w_riscv32 +#define helpet_vwmulu_vx_b helpet_vwmulu_vx_b_riscv32 +#define helpet_vwmulu_vx_h helpet_vwmulu_vx_h_riscv32 +#define helpet_vwmulu_vx_w helpet_vwmulu_vx_w_riscv32 +#define helpet_vwmulsu_vx_b helpet_vwmulsu_vx_b_riscv32 +#define helpet_vwmulsu_vx_h helpet_vwmulsu_vx_h_riscv32 +#define helpet_vwmulsu_vx_w helpet_vwmulsu_vx_w_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 00904765..2dae0034 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4191,6 +4191,24 @@ #define helper_vrem_vx_h helper_vrem_vx_h_riscv64 #define helper_vrem_vx_w helper_vrem_vx_w_riscv64 #define helper_vrem_vx_d helper_vrem_vx_d_riscv64 +#define helpet_vwmul_vv_b helpet_vwmul_vv_b_riscv64 +#define helpet_vwmul_vv_h helpet_vwmul_vv_h_riscv64 +#define helpet_vwmul_vv_w helpet_vwmul_vv_w_riscv64 +#define helpet_vwmulu_vv_b helpet_vwmulu_vv_b_riscv64 +#define helpet_vwmulu_vv_h helpet_vwmulu_vv_h_riscv64 +#define helpet_vwmulu_vv_w helpet_vwmulu_vv_w_riscv64 +#define helpet_vwmulsu_vv_b helpet_vwmulsu_vv_b_riscv64 +#define helpet_vwmulsu_vv_h helpet_vwmulsu_vv_h_riscv64 +#define helpet_vwmulsu_vv_w helpet_vwmulsu_vv_w_riscv64 +#define helpet_vwmul_vx_b helpet_vwmul_vx_b_riscv64 +#define helpet_vwmul_vx_h helpet_vwmul_vx_h_riscv64 +#define helpet_vwmul_vx_w helpet_vwmul_vx_w_riscv64 +#define helpet_vwmulu_vx_b helpet_vwmulu_vx_b_riscv64 +#define helpet_vwmulu_vx_h helpet_vwmulu_vx_h_riscv64 +#define helpet_vwmulu_vx_w helpet_vwmulu_vx_w_riscv64 +#define helpet_vwmulsu_vx_b helpet_vwmulsu_vx_b_riscv64 +#define helpet_vwmulsu_vx_h helpet_vwmulsu_vx_h_riscv64 +#define helpet_vwmulsu_vx_w helpet_vwmulsu_vx_w_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index e3d0c886..b0257a81 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -591,3 +591,22 @@ DEF_HELPER_6(vrem_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vwmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmul_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index 3d0ce375..d6254faa 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -375,6 +375,12 @@ vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm +vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm +vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm +vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm +vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm +vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm +vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 560e0735..78aa65a8 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -1522,3 +1522,11 @@ GEN_OPIVX_TRANS(vdivu_vx, opivx_check) GEN_OPIVX_TRANS(vdiv_vx, opivx_check) GEN_OPIVX_TRANS(vremu_vx, opivx_check) GEN_OPIVX_TRANS(vrem_vx, opivx_check) + +/* Vector Widening Integer Multiply Instructions */ +GEN_OPIVV_WIDEN_TRANS(vwmul_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmulu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmul_vx) +GEN_OPIVX_WIDEN_TRANS(vwmulu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 3ebf575a..12de329a 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -864,6 +864,18 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl) #define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t #define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t #define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t +#define WOP_UUU_B uint16_t, uint8_t, uint8_t, uint16_t, uint16_t +#define WOP_UUU_H uint32_t, uint16_t, uint16_t, uint32_t, uint32_t +#define WOP_UUU_W uint64_t, uint32_t, uint32_t, uint64_t, uint64_t +#define WOP_SSS_B int16_t, int8_t, int8_t, int16_t, int16_t +#define WOP_SSS_H int32_t, int16_t, int16_t, int32_t, int32_t +#define WOP_SSS_W int64_t, int32_t, int32_t, int64_t, int64_t +#define WOP_SUS_B int16_t, uint8_t, int8_t, uint16_t, int16_t +#define WOP_SUS_H int32_t, uint16_t, int16_t, uint32_t, int32_t +#define WOP_SUS_W int64_t, uint32_t, int32_t, uint64_t, int64_t +#define WOP_SSU_B int16_t, int8_t, uint8_t, int16_t, uint16_t +#define WOP_SSU_H int32_t, int16_t, uint16_t, int32_t, uint32_t +#define WOP_SSU_W int64_t, int32_t, uint32_t, int64_t, uint64_t /* operation of two vector elements */ typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i); @@ -1827,3 +1839,42 @@ GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb) GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh) GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl) GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq) + +/* Vector Widening Integer Multiply Instructions */ +RVVCALL(OPIVV2, vwmul_vv_b, WOP_SSS_B, H2, H1, H1, DO_MUL) +RVVCALL(OPIVV2, vwmul_vv_h, WOP_SSS_H, H4, H2, H2, DO_MUL) +RVVCALL(OPIVV2, vwmul_vv_w, WOP_SSS_W, H8, H4, H4, DO_MUL) +RVVCALL(OPIVV2, vwmulu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MUL) +RVVCALL(OPIVV2, vwmulu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MUL) +RVVCALL(OPIVV2, vwmulu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MUL) +RVVCALL(OPIVV2, vwmulsu_vv_b, WOP_SUS_B, H2, H1, H1, DO_MUL) +RVVCALL(OPIVV2, vwmulsu_vv_h, WOP_SUS_H, H4, H2, H2, DO_MUL) +RVVCALL(OPIVV2, vwmulsu_vv_w, WOP_SUS_W, H8, H4, H4, DO_MUL) +GEN_VEXT_VV(vwmul_vv_b, 1, 2, clearh) +GEN_VEXT_VV(vwmul_vv_h, 2, 4, clearl) +GEN_VEXT_VV(vwmul_vv_w, 4, 8, clearq) +GEN_VEXT_VV(vwmulu_vv_b, 1, 2, clearh) +GEN_VEXT_VV(vwmulu_vv_h, 2, 4, clearl) +GEN_VEXT_VV(vwmulu_vv_w, 4, 8, clearq) +GEN_VEXT_VV(vwmulsu_vv_b, 1, 2, clearh) +GEN_VEXT_VV(vwmulsu_vv_h, 2, 4, clearl) +GEN_VEXT_VV(vwmulsu_vv_w, 4, 8, clearq) + +RVVCALL(OPIVX2, vwmul_vx_b, WOP_SSS_B, H2, H1, DO_MUL) +RVVCALL(OPIVX2, vwmul_vx_h, WOP_SSS_H, H4, H2, DO_MUL) +RVVCALL(OPIVX2, vwmul_vx_w, WOP_SSS_W, H8, H4, DO_MUL) +RVVCALL(OPIVX2, vwmulu_vx_b, WOP_UUU_B, H2, H1, DO_MUL) +RVVCALL(OPIVX2, vwmulu_vx_h, WOP_UUU_H, H4, H2, DO_MUL) +RVVCALL(OPIVX2, vwmulu_vx_w, WOP_UUU_W, H8, H4, DO_MUL) +RVVCALL(OPIVX2, vwmulsu_vx_b, WOP_SUS_B, H2, H1, DO_MUL) +RVVCALL(OPIVX2, vwmulsu_vx_h, WOP_SUS_H, H4, H2, DO_MUL) +RVVCALL(OPIVX2, vwmulsu_vx_w, WOP_SUS_W, H8, H4, DO_MUL) +GEN_VEXT_VX(vwmul_vx_b, 1, 2, clearh) +GEN_VEXT_VX(vwmul_vx_h, 2, 4, clearl) +GEN_VEXT_VX(vwmul_vx_w, 4, 8, clearq) +GEN_VEXT_VX(vwmulu_vx_b, 1, 2, clearh) +GEN_VEXT_VX(vwmulu_vx_h, 2, 4, clearl) +GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq) +GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh) +GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl) +GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq)