From 45c297c99b5733a0960ed7c2e1eb7abd4e458b3a Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 5 Mar 2019 22:48:31 -0500 Subject: [PATCH] target/arm: Add set/clear_pstate_bits, share gen_ss_advance We do not need an out-of-line helper for manipulating bits in pstate. While changing things, share the implementation of gen_ss_advance. Backports commit 22ac3c49641f6eed93dca5b852030b4d3eacf6c4 from qemu --- qemu/aarch64.h | 1 - qemu/aarch64eb.h | 1 - qemu/arm.h | 1 - qemu/armeb.h | 1 - qemu/header_gen.py | 1 - qemu/m68k.h | 1 - qemu/mips.h | 1 - qemu/mips64.h | 1 - qemu/mips64el.h | 1 - qemu/mipsel.h | 1 - qemu/powerpc.h | 1 - qemu/sparc.h | 1 - qemu/sparc64.h | 1 - qemu/target/arm/helper.h | 2 -- qemu/target/arm/op_helper.c | 5 ----- qemu/target/arm/translate-a64.c | 12 ----------- qemu/target/arm/translate.c | 12 ----------- qemu/target/arm/translate.h | 37 +++++++++++++++++++++++++++++++++ qemu/x86_64.h | 1 - 19 files changed, 37 insertions(+), 45 deletions(-) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index fb2af47c..aeb78832 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_aarch64 #define helper_be_stq_mmu helper_be_stq_mmu_aarch64 #define helper_be_stw_mmu helper_be_stw_mmu_aarch64 -#define helper_clear_pstate_ss helper_clear_pstate_ss_aarch64 #define helper_clrsb_i32 helper_clrsb_i32_aarch64 #define helper_clrsb_i64 helper_clrsb_i64_aarch64 #define helper_clz_i32 helper_clz_i32_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 1076b743..e1b8b676 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_aarch64eb #define helper_be_stq_mmu helper_be_stq_mmu_aarch64eb #define helper_be_stw_mmu helper_be_stw_mmu_aarch64eb -#define helper_clear_pstate_ss helper_clear_pstate_ss_aarch64eb #define helper_clrsb_i32 helper_clrsb_i32_aarch64eb #define helper_clrsb_i64 helper_clrsb_i64_aarch64eb #define helper_clz_i32 helper_clz_i32_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index b219e32e..a1e33c0a 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_arm #define helper_be_stq_mmu helper_be_stq_mmu_arm #define helper_be_stw_mmu helper_be_stw_mmu_arm -#define helper_clear_pstate_ss helper_clear_pstate_ss_arm #define helper_clrsb_i32 helper_clrsb_i32_arm #define helper_clrsb_i64 helper_clrsb_i64_arm #define helper_clz_i32 helper_clz_i32_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index d3796b4c..673fca51 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_armeb #define helper_be_stq_mmu helper_be_stq_mmu_armeb #define helper_be_stw_mmu helper_be_stw_mmu_armeb -#define helper_clear_pstate_ss helper_clear_pstate_ss_armeb #define helper_clrsb_i32 helper_clrsb_i32_armeb #define helper_clrsb_i64 helper_clrsb_i64_armeb #define helper_clz_i32 helper_clz_i32_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 0abd4a58..b073b9dc 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -1070,7 +1070,6 @@ symbols = ( 'helper_be_stl_mmu', 'helper_be_stq_mmu', 'helper_be_stw_mmu', - 'helper_clear_pstate_ss', 'helper_clrsb_i32', 'helper_clrsb_i64', 'helper_clz_i32', diff --git a/qemu/m68k.h b/qemu/m68k.h index 420503cd..df416fd5 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_m68k #define helper_be_stq_mmu helper_be_stq_mmu_m68k #define helper_be_stw_mmu helper_be_stw_mmu_m68k -#define helper_clear_pstate_ss helper_clear_pstate_ss_m68k #define helper_clrsb_i32 helper_clrsb_i32_m68k #define helper_clrsb_i64 helper_clrsb_i64_m68k #define helper_clz_i32 helper_clz_i32_m68k diff --git a/qemu/mips.h b/qemu/mips.h index 63beda86..b1b9f637 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_mips #define helper_be_stq_mmu helper_be_stq_mmu_mips #define helper_be_stw_mmu helper_be_stw_mmu_mips -#define helper_clear_pstate_ss helper_clear_pstate_ss_mips #define helper_clrsb_i32 helper_clrsb_i32_mips #define helper_clrsb_i64 helper_clrsb_i64_mips #define helper_clz_i32 helper_clz_i32_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index e666c7e4..dc69ee2b 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_mips64 #define helper_be_stq_mmu helper_be_stq_mmu_mips64 #define helper_be_stw_mmu helper_be_stw_mmu_mips64 -#define helper_clear_pstate_ss helper_clear_pstate_ss_mips64 #define helper_clrsb_i32 helper_clrsb_i32_mips64 #define helper_clrsb_i64 helper_clrsb_i64_mips64 #define helper_clz_i32 helper_clz_i32_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 645211f1..84835476 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_mips64el #define helper_be_stq_mmu helper_be_stq_mmu_mips64el #define helper_be_stw_mmu helper_be_stw_mmu_mips64el -#define helper_clear_pstate_ss helper_clear_pstate_ss_mips64el #define helper_clrsb_i32 helper_clrsb_i32_mips64el #define helper_clrsb_i64 helper_clrsb_i64_mips64el #define helper_clz_i32 helper_clz_i32_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 89e7c3cf..967405b9 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_mipsel #define helper_be_stq_mmu helper_be_stq_mmu_mipsel #define helper_be_stw_mmu helper_be_stw_mmu_mipsel -#define helper_clear_pstate_ss helper_clear_pstate_ss_mipsel #define helper_clrsb_i32 helper_clrsb_i32_mipsel #define helper_clrsb_i64 helper_clrsb_i64_mipsel #define helper_clz_i32 helper_clz_i32_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index fa773362..ae74a823 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_powerpc #define helper_be_stq_mmu helper_be_stq_mmu_powerpc #define helper_be_stw_mmu helper_be_stw_mmu_powerpc -#define helper_clear_pstate_ss helper_clear_pstate_ss_powerpc #define helper_clrsb_i32 helper_clrsb_i32_powerpc #define helper_clrsb_i64 helper_clrsb_i64_powerpc #define helper_clz_i32 helper_clz_i32_powerpc diff --git a/qemu/sparc.h b/qemu/sparc.h index ad7ea035..26513875 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_sparc #define helper_be_stq_mmu helper_be_stq_mmu_sparc #define helper_be_stw_mmu helper_be_stw_mmu_sparc -#define helper_clear_pstate_ss helper_clear_pstate_ss_sparc #define helper_clrsb_i32 helper_clrsb_i32_sparc #define helper_clrsb_i64 helper_clrsb_i64_sparc #define helper_clz_i32 helper_clz_i32_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index 079016c1..838a2019 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_sparc64 #define helper_be_stq_mmu helper_be_stq_mmu_sparc64 #define helper_be_stw_mmu helper_be_stw_mmu_sparc64 -#define helper_clear_pstate_ss helper_clear_pstate_ss_sparc64 #define helper_clrsb_i32 helper_clrsb_i32_sparc64 #define helper_clrsb_i64 helper_clrsb_i64_sparc64 #define helper_clz_i32 helper_clz_i32_sparc64 diff --git a/qemu/target/arm/helper.h b/qemu/target/arm/helper.h index 376fd566..3a9db3d2 100644 --- a/qemu/target/arm/helper.h +++ b/qemu/target/arm/helper.h @@ -79,8 +79,6 @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) DEF_HELPER_2(get_cp_reg64, i64, env, ptr) -DEF_HELPER_1(clear_pstate_ss, void, env) - DEF_HELPER_2(get_r13_banked, i32, env, i32) DEF_HELPER_3(set_r13_banked, void, env, i32, i32) diff --git a/qemu/target/arm/op_helper.c b/qemu/target/arm/op_helper.c index efebfdc3..5351f342 100644 --- a/qemu/target/arm/op_helper.c +++ b/qemu/target/arm/op_helper.c @@ -841,11 +841,6 @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) return ri->readfn(env, ri); } -void HELPER(clear_pstate_ss)(CPUARMState *env) -{ - env->pstate &= ~PSTATE_SS; -} - void HELPER(pre_hvc)(CPUARMState *env) { ARMCPU *cpu = arm_env_get_cpu(env); diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index e08990cf..426c0fa9 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -448,18 +448,6 @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, s->base.is_jmp = DISAS_NORETURN; } -static void gen_ss_advance(DisasContext *s) -{ - TCGContext *tcg_ctx = s->uc->tcg_ctx; - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss = 0; - gen_helper_clear_pstate_ss(tcg_ctx, tcg_ctx->cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index ff2c7f7b..abdc52b4 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -299,18 +299,6 @@ static void gen_exception(DisasContext *s, int excp, uint32_t syndrome, uint32_t tcg_temp_free_i32(tcg_ctx, tcg_excp); } -static void gen_ss_advance(DisasContext *s) -{ - TCGContext *tcg_ctx = s->uc->tcg_ctx; - /* If the singlestep state is Active-not-pending, advance to - * Active-pending. - */ - if (s->ss_active) { - s->pstate_ss = 0; - gen_helper_clear_pstate_ss(tcg_ctx, tcg_ctx->cpu_env); - } -} - static void gen_step_complete_exception(DisasContext *s) { /* We just completed step of an insn. Move from Active-not-pending diff --git a/qemu/target/arm/translate.h b/qemu/target/arm/translate.h index f5ecdbf1..0a71ec72 100644 --- a/qemu/target/arm/translate.h +++ b/qemu/target/arm/translate.h @@ -202,6 +202,43 @@ static inline TCGv_i32 get_ahp_flag(DisasContext *s) return ret; } +/* Set bits within PSTATE. */ +static inline void set_pstate_bits(DisasContext *s, uint32_t bits) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + TCGv_i32 p = tcg_temp_new_i32(tcg_ctx); + + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + + tcg_gen_ld_i32(tcg_ctx, p, tcg_ctx->cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i32(tcg_ctx, p, p, bits); + tcg_gen_st_i32(tcg_ctx, p, tcg_ctx->cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(tcg_ctx, p); +} + +/* Clear bits within PSTATE. */ +static inline void clear_pstate_bits(DisasContext *s, uint32_t bits) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + TCGv_i32 p = tcg_temp_new_i32(tcg_ctx); + + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); + + tcg_gen_ld_i32(tcg_ctx, p, tcg_ctx->cpu_env, offsetof(CPUARMState, pstate)); + tcg_gen_andi_i32(tcg_ctx, p, p, ~bits); + tcg_gen_st_i32(tcg_ctx, p, tcg_ctx->cpu_env, offsetof(CPUARMState, pstate)); + tcg_temp_free_i32(tcg_ctx, p); +} + +/* If the singlestep state is Active-not-pending, advance to Active-pending. */ +static inline void gen_ss_advance(DisasContext *s) +{ + if (s->ss_active) { + s->pstate_ss = 0; + clear_pstate_bits(s, PSTATE_SS); + } +} + /* Vector operations shared between ARM and AArch64. */ extern const GVecGen3 bsl_op; extern const GVecGen3 bit_op; diff --git a/qemu/x86_64.h b/qemu/x86_64.h index f37abbcf..982d403c 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -1064,7 +1064,6 @@ #define helper_be_stl_mmu helper_be_stl_mmu_x86_64 #define helper_be_stq_mmu helper_be_stq_mmu_x86_64 #define helper_be_stw_mmu helper_be_stw_mmu_x86_64 -#define helper_clear_pstate_ss helper_clear_pstate_ss_x86_64 #define helper_clrsb_i32 helper_clrsb_i32_x86_64 #define helper_clrsb_i64 helper_clrsb_i64_x86_64 #define helper_clz_i32 helper_clz_i32_x86_64