From 4dd30ebfbd12eb5436c067b509c115776bb91592 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 18 Nov 2019 20:21:56 -0500 Subject: [PATCH] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB Use deposit as the composit operation to merge the bits from the two inputs. Backports commit d1f8755fc93911f5b27246b1da794542d222fa1b from qemu --- qemu/target/arm/translate.c | 26 ++++++++++---------------- 1 file changed, 10 insertions(+), 16 deletions(-) diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index aaad64d0..ffd4c737 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -8937,19 +8937,16 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) shift = (insn >> 7) & 0x1f; if (insn & (1 << 6)) { /* pkhtb */ - if (shift == 0) + if (shift == 0) { shift = 31; + } tcg_gen_sari_i32(tcg_ctx, tmp2, tmp2, shift); - tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0xffff0000); - tcg_gen_ext16u_i32(tcg_ctx, tmp2, tmp2); + tcg_gen_deposit_i32(tcg_ctx, tmp, tmp, tmp2, 0, 16); } else { /* pkhbt */ - if (shift) - tcg_gen_shli_i32(tcg_ctx, tmp2, tmp2, shift); - tcg_gen_ext16u_i32(tcg_ctx, tmp, tmp); - tcg_gen_andi_i32(tcg_ctx, tmp2, tmp2, 0xffff0000); + tcg_gen_shli_i32(tcg_ctx, tmp2, tmp2, shift); + tcg_gen_deposit_i32(tcg_ctx, tmp, tmp2, tmp, 0, 16); } - tcg_gen_or_i32(tcg_ctx, tmp, tmp, tmp2); tcg_temp_free_i32(tcg_ctx, tmp2); store_reg(s, rd, tmp); } else if ((insn & 0x00200020) == 0x00200000) { @@ -9981,19 +9978,16 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3); if (insn & (1 << 5)) { /* pkhtb */ - if (shift == 0) + if (shift == 0) { shift = 31; + } tcg_gen_sari_i32(tcg_ctx, tmp2, tmp2, shift); - tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 0xffff0000); - tcg_gen_ext16u_i32(tcg_ctx, tmp2, tmp2); + tcg_gen_deposit_i32(tcg_ctx, tmp, tmp, tmp2, 0, 16); } else { /* pkhbt */ - if (shift) - tcg_gen_shli_i32(tcg_ctx, tmp2, tmp2, shift); - tcg_gen_ext16u_i32(tcg_ctx, tmp, tmp); - tcg_gen_andi_i32(tcg_ctx, tmp2, tmp2, 0xffff0000); + tcg_gen_shli_i32(tcg_ctx, tmp2, tmp2, shift); + tcg_gen_deposit_i32(tcg_ctx, tmp, tmp2, tmp, 0, 16); } - tcg_gen_or_i32(tcg_ctx, tmp, tmp, tmp2); tcg_temp_free_i32(tcg_ctx, tmp2); store_reg(s, rd, tmp); } else {