From 4ea310c13171770714d396aface9710a14ecc50c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 8 Mar 2018 19:12:02 -0500 Subject: [PATCH] arm/translate-a64: add FP16 FRECPE Now we have added f16 during the re-factoring we can simply call the helper. Backports commit fbd06e1e4b6566b4d727f9e553c819d034942f68 from qemu --- qemu/target/arm/translate-a64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 398e3a15..cfb8df6c 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -11467,6 +11467,8 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6d: /* FCMLE (zero) */ handle_2misc_fcmp_zero(s, fpop, is_scalar, 0, is_q, MO_16, rn, rd); return; + case 0x3d: /* FRECPE */ + break; case 0x18: /* FRINTN */ need_rmode = true; only_in_vector = true; @@ -11586,6 +11588,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x3b: /* FCVTZS */ gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3d: /* FRECPE */ + gen_helper_recpe_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ @@ -11621,6 +11626,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x3b: /* FCVTZS */ gen_helper_advsimd_f16tosinth(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); break; + case 0x3d: /* FRECPE */ + gen_helper_recpe_f16(tcg_ctx, tcg_res, tcg_op, tcg_fpstatus); + break; case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */