yuzu-emu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-10-21 00:18:22 +02:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Flush tlb for ASID changes in EL2&0 translation regime

Browse Source 
Since we only support a single ASID, flush the tlb when it changes.

Note that TCR_EL2, like TCR_EL1, has the A1 bit that chooses between
the two TTBR* registers for the location of the ASID.

Backports commit d06dc93340825030b6297c61199a17c0067b0377 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 16:13:54 -04:00 committed by Lioncash
parent a2b8ebabfa
commit 50ac89852a
1 changed files with 15 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
qemu/target/arm/helper.c
View File

@ -3538,7 +3538,7 @@ static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
tcr->base_mask = 0xffffc000u; tcr->base_mask = 0xffffc000u;
} }
static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_tcr_el12_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
@ -3564,7 +3564,17 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* TODO: There are ASID fields in here with HCR_EL2.E2H */ /*
* If we are running with E2&0 regime, then an ASID is active.
* Flush if that might be changing. Note we're not checking
* TCR_EL2.A1 to know if this is really the TTBRx_EL2 that
* holds the active ASID, only checking the field that might.
*/
if (extract64(raw_read(env, ri) ^ value, 48, 16) &&
(arm_hcr_el2_eff(env) & HCR_E2H)) {
tlb_flush_by_mmuidx(env_cpu(env),
ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_0);
}
raw_write(env, ri, value); raw_write(env, ri, value);
} }
@ -3624,7 +3634,7 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
offsetof(CPUARMState, cp15.ttbr1_ns) } }, offsetof(CPUARMState, cp15.ttbr1_ns) } },
{ .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
.access = PL1_RW, .writefn = vmsa_tcr_el1_write, .access = PL1_RW, .writefn = vmsa_tcr_el12_write,
.resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write, .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) }, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[1]) },
{ .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2, { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
@ -4968,10 +4978,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.resetvalue = 0 }, .resetvalue = 0 },
{ .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
.access = PL2_RW, .access = PL2_RW, .writefn = vmsa_tcr_el12_write,
/* no .writefn needed as this can't cause an ASID change; /* no .raw_writefn or .resetfn needed as we never use mask/base_mask */
* no .raw_writefn or .resetfn needed as we never use mask/base_mask
*/
.fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) },
{ .name = "VTCR", .state = ARM_CP_STATE_AA32, { .name = "VTCR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2,