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target/arm: Flush high bits of sve register after AdvSIMD INS

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Writes to AdvSIMD registers flush the bits above 128.

Backports commit 528dc354b6f3aa82d65141cc60bc0e725e6cae98 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:58:07 -04:00 committed by Lioncash
parent 74cbfceb56
commit 51b6064ba4
1 changed files with 6 additions and 0 deletions
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6
qemu/target/arm/translate-a64.c
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@ -7674,6 +7674,9 @@ static void handle_simd_inse(DisasContext *s, int rd, int rn,
write_vec_element(s, tmp, rd, dst_index, size); write_vec_element(s, tmp, rd, dst_index, size);
tcg_temp_free_i64(tcg_ctx, tmp); tcg_temp_free_i64(tcg_ctx, tmp);
/* INS is considered a 128-bit write for SVE. */
clear_vec_high(s, true, rd);
} }
@ -7703,6 +7706,9 @@ static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
idx = extract32(imm5, 1 + size, 4 - size); idx = extract32(imm5, 1 + size, 4 - size);
write_vec_element(s, cpu_reg(s, rn), rd, idx, size); write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
/* INS is considered a 128-bit write for SVE. */
clear_vec_high(s, true, rd);
} }
/* /*