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target/arm: Implement SVE copy to vector (predicated)

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Backports commit 792a557847697235037fea30eaaacb9b45b4c9e5 from qemu
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Richard Henderson 2018-06-15 13:03:33 -04:00 committed by Lioncash
parent 0bb2fdd752
commit 53d151de58
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GPG Key ID: 4E3C3CC1031BA9C7
2 changed files with 26 additions and 0 deletions
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6
qemu/target/arm/sve.decode
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@ -450,6 +450,12 @@ LASTB_v 00000101 .. 10001 1 100 ... ..... ..... @rd_pg_rn
LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn LASTA_r 00000101 .. 10000 0 101 ... ..... ..... @rd_pg_rn
LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn LASTB_r 00000101 .. 10000 1 101 ... ..... ..... @rd_pg_rn
# SVE copy element from SIMD&FP scalar register
CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn
# SVE copy element from general register to vector (predicated)
CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn
### SVE Predicate Logical Operations Group ### SVE Predicate Logical Operations Group
# SVE predicate logical operations # SVE predicate logical operations

20
qemu/target/arm/translate-sve.c
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@ -2724,6 +2724,26 @@ static bool trans_LASTB_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
return do_last_general(s, a, true); return do_last_general(s, a, true);
} }
static bool trans_CPY_m_r(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
if (sve_access_check(s)) {
do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, cpu_reg_sp(s, a->rn));
}
return true;
}
static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
{
if (sve_access_check(s)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int ofs = vec_reg_offset(s, a->rn, 0, a->esz);
TCGv_i64 t = load_esz(s, tcg_ctx->cpu_env, ofs, a->esz);
do_cpy_m(s, a->esz, a->rd, a->rd, a->pg, t);
tcg_temp_free_i64(tcg_ctx, t);
}
return true;
}
/* /*
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group *** SVE Memory - 32-bit Gather and Unsized Contiguous Group
*/ */