From 55a3c5a4a54963ef517ca3c4b88e3d9ca0782f4f Mon Sep 17 00:00:00 2001
From: meta <27898374+hosaka-corp@users.noreply.github.com>
Date: Tue, 14 Jan 2020 09:37:10 -0500
Subject: [PATCH] Expose different 32-bit ARM CPU models to users via UC_MODE
 flags (#1165)

Backports commit ba745521991429b76b93180dca70c294c6b343cf from unicorn.
---
 include/uc_priv.h         |  3 ++-
 include/unicorn/unicorn.h | 14 +++++++++++++-
 qemu/hw/arm/tosa.c        |  6 ++++++
 3 files changed, 21 insertions(+), 2 deletions(-)

diff --git a/include/uc_priv.h b/include/uc_priv.h
index 01b4cff3..c9772b25 100644
--- a/include/uc_priv.h
+++ b/include/uc_priv.h
@@ -14,7 +14,8 @@
 
 // These are masks of supported modes for each cpu/arch.
 // They should be updated when changes are made to the uc_mode enum typedef.
-#define UC_MODE_ARM_MASK    (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN|UC_MODE_MCLASS|UC_MODE_BIG_ENDIAN)
+#define UC_MODE_ARM_MASK    (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN|UC_MODE_MCLASS | \
+                             UC_MODE_ARM926|UC_MODE_ARM946|UC_MODE_ARM1176|UC_MODE_BIG_ENDIAN)
 #define UC_MODE_M68K_MASK   (UC_MODE_BIG_ENDIAN)
 #define UC_MODE_MIPS_MASK   (UC_MODE_MIPS32|UC_MODE_MIPS64|UC_MODE_LITTLE_ENDIAN|UC_MODE_BIG_ENDIAN)
 #define UC_MODE_PPC_MASK    (UC_MODE_PPC64|UC_MODE_BIG_ENDIAN)
diff --git a/include/unicorn/unicorn.h b/include/unicorn/unicorn.h
index 6221e86c..91aa2638 100644
--- a/include/unicorn/unicorn.h
+++ b/include/unicorn/unicorn.h
@@ -104,31 +104,43 @@ typedef enum uc_arch {
 typedef enum uc_mode {
     UC_MODE_LITTLE_ENDIAN = 0,    // little-endian mode (default mode)
     UC_MODE_BIG_ENDIAN = 1 << 30, // big-endian mode
+
     // arm / arm64
     UC_MODE_ARM = 0,              // ARM mode
     UC_MODE_THUMB = 1 << 4,       // THUMB mode (including Thumb-2)
     UC_MODE_MCLASS = 1 << 5,      // ARM's Cortex-M series (currently unsupported)
     UC_MODE_V8 = 1 << 6,          // ARMv8 A32 encodings for ARM (currently unsupported)
+
+    // arm (32bit) cpu types
+    UC_MODE_ARM926 = 1 << 7,    // ARM926 CPU type
+    UC_MODE_ARM946 = 1 << 8,    // ARM946 CPU type
+    UC_MODE_ARM1176 = 1 << 9,   // ARM1176 CPU type
+
     // mips
     UC_MODE_MICRO = 1 << 4,       // MicroMips mode (currently unsupported)
     UC_MODE_MIPS3 = 1 << 5,       // Mips III ISA (currently unsupported)
     UC_MODE_MIPS32R6 = 1 << 6,    // Mips32r6 ISA (currently unsupported)
     UC_MODE_MIPS32 = 1 << 2,      // Mips32 ISA
     UC_MODE_MIPS64 = 1 << 3,      // Mips64 ISA
+
     // x86 / x64
     UC_MODE_16 = 1 << 1,          // 16-bit mode
     UC_MODE_32 = 1 << 2,          // 32-bit mode
     UC_MODE_64 = 1 << 3,          // 64-bit mode
-    // ppc 
+
+    // ppc
     UC_MODE_PPC32 = 1 << 2,       // 32-bit mode (currently unsupported)
     UC_MODE_PPC64 = 1 << 3,       // 64-bit mode (currently unsupported)
     UC_MODE_QPX = 1 << 4,         // Quad Processing eXtensions mode (currently unsupported)
+
     // sparc
     UC_MODE_SPARC32 = 1 << 2,     // 32-bit mode
     UC_MODE_SPARC64 = 1 << 3,     // 64-bit mode
     UC_MODE_V9 = 1 << 4,          // SparcV9 mode (currently unsupported)
+
     // m68k
     // No flags for M68K yet
+
     // RISC-V
     UC_MODE_RISCV32 = 1 << 2,     // 32-bit mode
     UC_MODE_RISCV64 = 1 << 3,     // 64-bit mode
diff --git a/qemu/hw/arm/tosa.c b/qemu/hw/arm/tosa.c
index bff4473c..8f30e9c9 100644
--- a/qemu/hw/arm/tosa.c
+++ b/qemu/hw/arm/tosa.c
@@ -33,6 +33,12 @@ static void tosa_machine_init(struct uc_struct *uc, MachineClass *mc)
 
     if (uc->mode & UC_MODE_MCLASS) {
         mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-m3");
+    } else if (uc->mode & UC_MODE_ARM926) {
+        mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm926");
+    } else if (uc->mode & UC_MODE_ARM946) {
+        mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm946");
+    } else if (uc->mode & UC_MODE_ARM1176) {
+        mc->default_cpu_type = ARM_CPU_TYPE_NAME("arm1176");
     } else {
         // Unicorn: Enable all CPU features
         mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");