From 5812f7e3a317a6d166d6879c0628f37013ae1145 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 8 Mar 2018 09:37:53 -0500 Subject: [PATCH] target/arm: Implement writing to CONTROL_NS for v8M In commit 50f11062d4c896 we added support for MSR/MRS access to the NS banked special registers, but we forgot to implement the support for writing to CONTROL_NS. Correct the omission. Backports commit 6eb3a64e2a96f5ced1f7896042b01f002bf0a91f from qemu --- qemu/target/arm/helper.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index 4f648abe..a592de6c 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -9681,6 +9681,16 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) } env->v7m.faultmask[M_REG_NS] = val & 1; return; + case 0x94: /* CONTROL_NS */ + if (!env->v7m.secure) { + return; + } + write_v7m_control_spsel_for_secstate(env, + val & R_V7M_CONTROL_SPSEL_MASK, + M_REG_NS); + env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK; + env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK; + return; case 0x98: /* SP_NS */ { /* This gives the non-secure SP selected based on whether we're