fpu/softfloat: re-factor add/sub

We can now add float16_add/sub and use the common decompose and
canonicalize functions to have a single implementation for
float16/32/64 add and sub functions.

Backports commit 6fff216769cf7eaa3961c85dee7a72838696d365 from qemu

qemu/aarch64.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_aarch64
 #define float128_unordered_quiet float128_unordered_quiet_aarch64
 #define float16ToCommonNaN float16ToCommonNaN_aarch64
+#define float16_add float16_add_aarch64
 #define float16_default_nan float16_default_nan_aarch64
 #define float16_is_quiet_nan float16_is_quiet_nan_aarch64
 #define float16_is_signaling_nan float16_is_signaling_nan_aarch64
 #define float16_maybe_silence_nan float16_maybe_silence_nan_aarch64
 #define float16_squash_input_denormal float16_squash_input_denormal_aarch64
+#define float16_sub float16_sub_aarch64
 #define float16_to_float32 float16_to_float32_aarch64
 #define float16_to_float64 float16_to_float64_aarch64
 #define float32ToCommonNaN float32ToCommonNaN_aarch64

qemu/aarch64eb.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_aarch64eb
 #define float128_unordered_quiet float128_unordered_quiet_aarch64eb
 #define float16ToCommonNaN float16ToCommonNaN_aarch64eb
+#define float16_add float16_add_aarch64eb
 #define float16_default_nan float16_default_nan_aarch64eb
 #define float16_is_quiet_nan float16_is_quiet_nan_aarch64eb
 #define float16_is_signaling_nan float16_is_signaling_nan_aarch64eb
 #define float16_maybe_silence_nan float16_maybe_silence_nan_aarch64eb
 #define float16_squash_input_denormal float16_squash_input_denormal_aarch64eb
+#define float16_sub float16_sub_aarch64eb
 #define float16_to_float32 float16_to_float32_aarch64eb
 #define float16_to_float64 float16_to_float64_aarch64eb
 #define float32ToCommonNaN float32ToCommonNaN_aarch64eb

qemu/arm.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_arm
 #define float128_unordered_quiet float128_unordered_quiet_arm
 #define float16ToCommonNaN float16ToCommonNaN_arm
+#define float16_add float16_add_arm
 #define float16_default_nan float16_default_nan_arm
 #define float16_is_quiet_nan float16_is_quiet_nan_arm
 #define float16_is_signaling_nan float16_is_signaling_nan_arm
 #define float16_maybe_silence_nan float16_maybe_silence_nan_arm
 #define float16_squash_input_denormal float16_squash_input_denormal_arm
+#define float16_sub float16_sub_arm
 #define float16_to_float32 float16_to_float32_arm
 #define float16_to_float64 float16_to_float64_arm
 #define float32ToCommonNaN float32ToCommonNaN_arm

qemu/armeb.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_armeb
 #define float128_unordered_quiet float128_unordered_quiet_armeb
 #define float16ToCommonNaN float16ToCommonNaN_armeb
+#define float16_add float16_add_armeb
 #define float16_default_nan float16_default_nan_armeb
 #define float16_is_quiet_nan float16_is_quiet_nan_armeb
 #define float16_is_signaling_nan float16_is_signaling_nan_armeb
 #define float16_maybe_silence_nan float16_maybe_silence_nan_armeb
 #define float16_squash_input_denormal float16_squash_input_denormal_armeb
+#define float16_sub float16_sub_armeb
 #define float16_to_float32 float16_to_float32_armeb
 #define float16_to_float64 float16_to_float64_armeb
 #define float32ToCommonNaN float32ToCommonNaN_armeb

qemu/fpu/softfloat.c

@@ -2515,218 +2515,6 @@ float32 float32_round_to_int(float32 a, float_status *status)
 
 }
 
-/*----------------------------------------------------------------------------
-| Returns the result of adding the absolute values of the single-precision
-| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated
-| before being returned.  `zSign' is ignored if the result is a NaN.
-| The addition is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static float32 addFloat32Sigs(float32 a, float32 b, flag zSign, float_status *status)
-{
-    int aExp, bExp, zExp;
-    uint32_t aSig, bSig, zSig;
-    int expDiff;
-
-    aSig = extractFloat32Frac( a );
-    aExp = extractFloat32Exp( a );
-    bSig = extractFloat32Frac( b );
-    bExp = extractFloat32Exp( b );
-    expDiff = aExp - bExp;
-    aSig <<= 6;
-    bSig <<= 6;
-    if ( 0 < expDiff ) {
-        if ( aExp == 0xFF ) {
-            if (aSig) {
-                return propagateFloat32NaN(a, b, status);
-            }
-            return a;
-        }
-        if ( bExp == 0 ) {
-            --expDiff;
-        }
-        else {
-            bSig |= 0x20000000;
-        }
-        shift32RightJamming( bSig, expDiff, &bSig );
-        zExp = aExp;
-    }
-    else if ( expDiff < 0 ) {
-        if ( bExp == 0xFF ) {
-            if (bSig) {
-                return propagateFloat32NaN(a, b, status);
-            }
-            return packFloat32( zSign, 0xFF, 0 );
-        }
-        if ( aExp == 0 ) {
-            ++expDiff;
-        }
-        else {
-            aSig |= 0x20000000;
-        }
-        shift32RightJamming( aSig, - expDiff, &aSig );
-        zExp = bExp;
-    }
-    else {
-        if ( aExp == 0xFF ) {
-            if (aSig | bSig) {
-                return propagateFloat32NaN(a, b, status);
-            }
-            return a;
-        }
-        if ( aExp == 0 ) {
-            if (status->flush_to_zero) {
-                if (aSig | bSig) {
-                    float_raise(float_flag_output_denormal, status);
-                }
-                return packFloat32(zSign, 0, 0);
-            }
-            return packFloat32( zSign, 0, ( aSig + bSig )>>6 );
-        }
-        zSig = 0x40000000 + aSig + bSig;
-        zExp = aExp;
-        goto roundAndPack;
-    }
-    aSig |= 0x20000000;
-    zSig = ( aSig + bSig )<<1;
-    --zExp;
-    if ( (int32_t) zSig < 0 ) {
-        zSig = aSig + bSig;
-        ++zExp;
-    }
- roundAndPack:
-    return roundAndPackFloat32( zSign, zExp, zSig, status );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of subtracting the absolute values of the single-
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the
-| difference is negated before being returned.  `zSign' is ignored if the
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE
-| Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static float32 subFloat32Sigs(float32 a, float32 b, flag zSign, float_status *status)
-{
-    int aExp, bExp, zExp;
-    uint32_t aSig, bSig, zSig;
-    int expDiff;
-
-    aSig = extractFloat32Frac( a );
-    aExp = extractFloat32Exp( a );
-    bSig = extractFloat32Frac( b );
-    bExp = extractFloat32Exp( b );
-    expDiff = aExp - bExp;
-    aSig <<= 7;
-    bSig <<= 7;
-    if ( 0 < expDiff ) goto aExpBigger;
-    if ( expDiff < 0 ) goto bExpBigger;
-    if ( aExp == 0xFF ) {
-        if (aSig | bSig) {
-            return propagateFloat32NaN(a, b, status);
-        }
-        float_raise(float_flag_invalid, status);
-        return float32_default_nan(status);
-    }
-    if ( aExp == 0 ) {
-        aExp = 1;
-        bExp = 1;
-    }
-    if ( bSig < aSig ) goto aBigger;
-    if ( aSig < bSig ) goto bBigger;
-    return packFloat32( status->float_rounding_mode == float_round_down, 0, 0 );
- bExpBigger:
-    if ( bExp == 0xFF ) {
-        if (bSig) {
-            return propagateFloat32NaN(a, b, status);
-        }
-        return packFloat32( zSign ^ 1, 0xFF, 0 );
-    }
-    if ( aExp == 0 ) {
-        ++expDiff;
-    }
-    else {
-        aSig |= 0x40000000;
-    }
-    shift32RightJamming( aSig, - expDiff, &aSig );
-    bSig |= 0x40000000;
- bBigger:
-    zSig = bSig - aSig;
-    zExp = bExp;
-    zSign ^= 1;
-    goto normalizeRoundAndPack;
- aExpBigger:
-    if ( aExp == 0xFF ) {
-        if (aSig) {
-            return propagateFloat32NaN(a, b, status);
-        }
-        return a;
-    }
-    if ( bExp == 0 ) {
-        --expDiff;
-    }
-    else {
-        bSig |= 0x40000000;
-    }
-    shift32RightJamming( bSig, expDiff, &bSig );
-    aSig |= 0x40000000;
- aBigger:
-    zSig = aSig - bSig;
-    zExp = aExp;
- normalizeRoundAndPack:
-    --zExp;
-    return normalizeRoundAndPackFloat32( zSign, zExp, zSig, status );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of adding the single-precision floating-point values `a'
-| and `b'.  The operation is performed according to the IEC/IEEE Standard for
-| Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float32 float32_add(float32 a, float32 b, float_status *status)
-{
-    flag aSign, bSign;
-    a = float32_squash_input_denormal(a, status);
-    b = float32_squash_input_denormal(b, status);
-
-    aSign = extractFloat32Sign( a );
-    bSign = extractFloat32Sign( b );
-    if ( aSign == bSign ) {
-        return addFloat32Sigs( a, b, aSign, status);
-    }
-    else {
-        return subFloat32Sigs( a, b, aSign, status );
-    }
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of subtracting the single-precision floating-point values
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard
-| for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float32 float32_sub(float32 a, float32 b, float_status *status)
-{
-    flag aSign, bSign;
-    a = float32_squash_input_denormal(a, status);
-    b = float32_squash_input_denormal(b, status);
-
-    aSign = extractFloat32Sign( a );
-    bSign = extractFloat32Sign( b );
-    if ( aSign == bSign ) {
-        return subFloat32Sigs( a, b, aSign, status );
-    }
-    else {
-        return addFloat32Sigs( a, b, aSign, status );
-    }
-
-}
-
 /*----------------------------------------------------------------------------
 | Returns the result of multiplying the single-precision floating-point values
 | `a' and `b'.  The operation is performed according to the IEC/IEEE Standard
@@ -2749,11 +2537,12 @@ float32 float32_mul(float32 a, float32 b, float_status *status)
     aSign = extractFloat32Sign( a );
     bSig = extractFloat32Frac( b );
     bExp = extractFloat32Exp( b );
+
     bSign = extractFloat32Sign( b );
     zSign = aSign ^ bSign;
     if ( aExp == 0xFF ) {
         if ( aSig || ( ( bExp == 0xFF ) && bSig ) ) {
-            return propagateFloat32NaN( a, b, status );
+            return propagateFloat32NaN(a, b, status);
         }
         if ( ( bExp | bSig ) == 0 ) {
             float_raise(float_flag_invalid, status);
@@ -4320,218 +4109,6 @@ float64 float64_trunc_to_int(float64 a, float_status *status)
     return res;
 }
 
-/*----------------------------------------------------------------------------
-| Returns the result of adding the absolute values of the double-precision
-| floating-point values `a' and `b'.  If `zSign' is 1, the sum is negated
-| before being returned.  `zSign' is ignored if the result is a NaN.
-| The addition is performed according to the IEC/IEEE Standard for Binary
-| Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static float64 addFloat64Sigs(float64 a, float64 b, flag zSign, float_status *status)
-{
-    int aExp, bExp, zExp;
-    uint64_t aSig, bSig, zSig;
-    int expDiff;
-
-    aSig = extractFloat64Frac( a );
-    aExp = extractFloat64Exp( a );
-    bSig = extractFloat64Frac( b );
-    bExp = extractFloat64Exp( b );
-    expDiff = aExp - bExp;
-    aSig <<= 9;
-    bSig <<= 9;
-    if ( 0 < expDiff ) {
-        if ( aExp == 0x7FF ) {
-            if (aSig) {
-                return propagateFloat64NaN(a, b, status);
-            }
-            return a;
-        }
-        if ( bExp == 0 ) {
-            --expDiff;
-        }
-        else {
-            bSig |= LIT64( 0x2000000000000000 );
-        }
-        shift64RightJamming( bSig, expDiff, &bSig );
-        zExp = aExp;
-    }
-    else if ( expDiff < 0 ) {
-        if ( bExp == 0x7FF ) {
-            if (bSig) {
-                return propagateFloat64NaN(a, b, status);
-            }
-            return packFloat64( zSign, 0x7FF, 0 );
-        }
-        if ( aExp == 0 ) {
-            ++expDiff;
-        }
-        else {
-            aSig |= LIT64( 0x2000000000000000 );
-        }
-        shift64RightJamming( aSig, - expDiff, &aSig );
-        zExp = bExp;
-    }
-    else {
-        if ( aExp == 0x7FF ) {
-            if (aSig | bSig) {
-                return propagateFloat64NaN(a, b, status);
-            }
-            return a;
-        }
-        if ( aExp == 0 ) {
-            if (status->flush_to_zero) {
-                if (aSig | bSig) {
-                    float_raise(float_flag_output_denormal, status);
-                }
-                return packFloat64(zSign, 0, 0);
-            }
-            return packFloat64( zSign, 0, ( aSig + bSig )>>9 );
-        }
-        zSig = LIT64( 0x4000000000000000 ) + aSig + bSig;
-        zExp = aExp;
-        goto roundAndPack;
-    }
-    aSig |= LIT64( 0x2000000000000000 );
-    zSig = ( aSig + bSig )<<1;
-    --zExp;
-    if ( (int64_t) zSig < 0 ) {
-        zSig = aSig + bSig;
-        ++zExp;
-    }
- roundAndPack:
-    return roundAndPackFloat64( zSign, zExp, zSig, status );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of subtracting the absolute values of the double-
-| precision floating-point values `a' and `b'.  If `zSign' is 1, the
-| difference is negated before being returned.  `zSign' is ignored if the
-| result is a NaN.  The subtraction is performed according to the IEC/IEEE
-| Standard for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-static float64 subFloat64Sigs(float64 a, float64 b, flag zSign, float_status *status)
-{
-    int aExp, bExp, zExp;
-    uint64_t aSig, bSig, zSig;
-    int expDiff;
-
-    aSig = extractFloat64Frac( a );
-    aExp = extractFloat64Exp( a );
-    bSig = extractFloat64Frac( b );
-    bExp = extractFloat64Exp( b );
-    expDiff = aExp - bExp;
-    aSig <<= 10;
-    bSig <<= 10;
-    if ( 0 < expDiff ) goto aExpBigger;
-    if ( expDiff < 0 ) goto bExpBigger;
-    if ( aExp == 0x7FF ) {
-        if (aSig | bSig) {
-            return propagateFloat64NaN(a, b, status);
-        }
-        float_raise(float_flag_invalid, status);
-        return float64_default_nan(status);
-    }
-    if ( aExp == 0 ) {
-        aExp = 1;
-        bExp = 1;
-    }
-    if ( bSig < aSig ) goto aBigger;
-    if ( aSig < bSig ) goto bBigger;
-    return packFloat64( status->float_rounding_mode == float_round_down, 0, 0 );
- bExpBigger:
-    if ( bExp == 0x7FF ) {
-        if (bSig) {
-            return propagateFloat64NaN(a, b, status);
-        }
-        return packFloat64( zSign ^ 1, 0x7FF, 0 );
-    }
-    if ( aExp == 0 ) {
-        ++expDiff;
-    }
-    else {
-        aSig |= LIT64( 0x4000000000000000 );
-    }
-    shift64RightJamming( aSig, - expDiff, &aSig );
-    bSig |= LIT64( 0x4000000000000000 );
- bBigger:
-    zSig = bSig - aSig;
-    zExp = bExp;
-    zSign ^= 1;
-    goto normalizeRoundAndPack;
- aExpBigger:
-    if ( aExp == 0x7FF ) {
-        if (aSig) {
-            return propagateFloat64NaN(a, b, status);
-        }
-        return a;
-    }
-    if ( bExp == 0 ) {
-        --expDiff;
-    }
-    else {
-        bSig |= LIT64( 0x4000000000000000 );
-    }
-    shift64RightJamming( bSig, expDiff, &bSig );
-    aSig |= LIT64( 0x4000000000000000 );
- aBigger:
-    zSig = aSig - bSig;
-    zExp = aExp;
- normalizeRoundAndPack:
-    --zExp;
-    return normalizeRoundAndPackFloat64( zSign, zExp, zSig, status );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of adding the double-precision floating-point values `a'
-| and `b'.  The operation is performed according to the IEC/IEEE Standard for
-| Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float64 float64_add(float64 a, float64 b, float_status *status)
-{
-    flag aSign, bSign;
-    a = float64_squash_input_denormal(a, status);
-    b = float64_squash_input_denormal(b, status);
-
-    aSign = extractFloat64Sign( a );
-    bSign = extractFloat64Sign( b );
-    if ( aSign == bSign ) {
-        return addFloat64Sigs( a, b, aSign, status );
-    }
-    else {
-        return subFloat64Sigs( a, b, aSign, status );
-    }
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the result of subtracting the double-precision floating-point values
-| `a' and `b'.  The operation is performed according to the IEC/IEEE Standard
-| for Binary Floating-Point Arithmetic.
-*----------------------------------------------------------------------------*/
-
-float64 float64_sub(float64 a, float64 b, float_status *status)
-{
-    flag aSign, bSign;
-    a = float64_squash_input_denormal(a, status);
-    b = float64_squash_input_denormal(b, status);
-
-    aSign = extractFloat64Sign( a );
-    bSign = extractFloat64Sign( b );
-    if ( aSign == bSign ) {
-        return subFloat64Sigs( a, b, aSign, status );
-    }
-    else {
-        return addFloat64Sigs( a, b, aSign, status );
-    }
-
-}
-
 /*----------------------------------------------------------------------------
 | Returns the result of multiplying the double-precision floating-point values
 | `a' and `b'.  The operation is performed according to the IEC/IEEE Standard

qemu/header_gen.py

@@ -493,11 +493,13 @@ symbols = (
     'float128_unordered',
     'float128_unordered_quiet',
     'float16ToCommonNaN',
+    'float16_add',
     'float16_default_nan',
     'float16_is_quiet_nan',
     'float16_is_signaling_nan',
     'float16_maybe_silence_nan',
     'float16_squash_input_denormal',
+    'float16_sub',
     'float16_to_float32',
     'float16_to_float64',
     'float32ToCommonNaN',

qemu/include/fpu/softfloat.h

@@ -243,6 +243,10 @@ float64 float16_to_float64(float16 a, flag ieee, float_status *status);
 /*----------------------------------------------------------------------------
 | Software half-precision operations.
 *----------------------------------------------------------------------------*/
+
+float16 float16_add(float16, float16, float_status *status);
+float16 float16_sub(float16, float16, float_status *status);
+
 int float16_is_quiet_nan(float16, float_status *status);
 int float16_is_signaling_nan(float16, float_status *status);
 float16 float16_maybe_silence_nan(float16, float_status *status);

qemu/m68k.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_m68k
 #define float128_unordered_quiet float128_unordered_quiet_m68k
 #define float16ToCommonNaN float16ToCommonNaN_m68k
+#define float16_add float16_add_m68k
 #define float16_default_nan float16_default_nan_m68k
 #define float16_is_quiet_nan float16_is_quiet_nan_m68k
 #define float16_is_signaling_nan float16_is_signaling_nan_m68k
 #define float16_maybe_silence_nan float16_maybe_silence_nan_m68k
 #define float16_squash_input_denormal float16_squash_input_denormal_m68k
+#define float16_sub float16_sub_m68k
 #define float16_to_float32 float16_to_float32_m68k
 #define float16_to_float64 float16_to_float64_m68k
 #define float32ToCommonNaN float32ToCommonNaN_m68k

qemu/mips.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_mips
 #define float128_unordered_quiet float128_unordered_quiet_mips
 #define float16ToCommonNaN float16ToCommonNaN_mips
+#define float16_add float16_add_mips
 #define float16_default_nan float16_default_nan_mips
 #define float16_is_quiet_nan float16_is_quiet_nan_mips
 #define float16_is_signaling_nan float16_is_signaling_nan_mips
 #define float16_maybe_silence_nan float16_maybe_silence_nan_mips
 #define float16_squash_input_denormal float16_squash_input_denormal_mips
+#define float16_sub float16_sub_mips
 #define float16_to_float32 float16_to_float32_mips
 #define float16_to_float64 float16_to_float64_mips
 #define float32ToCommonNaN float32ToCommonNaN_mips

qemu/mips64.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_mips64
 #define float128_unordered_quiet float128_unordered_quiet_mips64
 #define float16ToCommonNaN float16ToCommonNaN_mips64
+#define float16_add float16_add_mips64
 #define float16_default_nan float16_default_nan_mips64
 #define float16_is_quiet_nan float16_is_quiet_nan_mips64
 #define float16_is_signaling_nan float16_is_signaling_nan_mips64
 #define float16_maybe_silence_nan float16_maybe_silence_nan_mips64
 #define float16_squash_input_denormal float16_squash_input_denormal_mips64
+#define float16_sub float16_sub_mips64
 #define float16_to_float32 float16_to_float32_mips64
 #define float16_to_float64 float16_to_float64_mips64
 #define float32ToCommonNaN float32ToCommonNaN_mips64

qemu/mips64el.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_mips64el
 #define float128_unordered_quiet float128_unordered_quiet_mips64el
 #define float16ToCommonNaN float16ToCommonNaN_mips64el
+#define float16_add float16_add_mips64el
 #define float16_default_nan float16_default_nan_mips64el
 #define float16_is_quiet_nan float16_is_quiet_nan_mips64el
 #define float16_is_signaling_nan float16_is_signaling_nan_mips64el
 #define float16_maybe_silence_nan float16_maybe_silence_nan_mips64el
 #define float16_squash_input_denormal float16_squash_input_denormal_mips64el
+#define float16_sub float16_sub_mips64el
 #define float16_to_float32 float16_to_float32_mips64el
 #define float16_to_float64 float16_to_float64_mips64el
 #define float32ToCommonNaN float32ToCommonNaN_mips64el

qemu/mipsel.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_mipsel
 #define float128_unordered_quiet float128_unordered_quiet_mipsel
 #define float16ToCommonNaN float16ToCommonNaN_mipsel
+#define float16_add float16_add_mipsel
 #define float16_default_nan float16_default_nan_mipsel
 #define float16_is_quiet_nan float16_is_quiet_nan_mipsel
 #define float16_is_signaling_nan float16_is_signaling_nan_mipsel
 #define float16_maybe_silence_nan float16_maybe_silence_nan_mipsel
 #define float16_squash_input_denormal float16_squash_input_denormal_mipsel
+#define float16_sub float16_sub_mipsel
 #define float16_to_float32 float16_to_float32_mipsel
 #define float16_to_float64 float16_to_float64_mipsel
 #define float32ToCommonNaN float32ToCommonNaN_mipsel

qemu/powerpc.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_powerpc
 #define float128_unordered_quiet float128_unordered_quiet_powerpc
 #define float16ToCommonNaN float16ToCommonNaN_powerpc
+#define float16_add float16_add_powerpc
 #define float16_default_nan float16_default_nan_powerpc
 #define float16_is_quiet_nan float16_is_quiet_nan_powerpc
 #define float16_is_signaling_nan float16_is_signaling_nan_powerpc
 #define float16_maybe_silence_nan float16_maybe_silence_nan_powerpc
 #define float16_squash_input_denormal float16_squash_input_denormal_powerpc
+#define float16_sub float16_sub_powerpc
 #define float16_to_float32 float16_to_float32_powerpc
 #define float16_to_float64 float16_to_float64_powerpc
 #define float32ToCommonNaN float32ToCommonNaN_powerpc

qemu/sparc.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_sparc
 #define float128_unordered_quiet float128_unordered_quiet_sparc
 #define float16ToCommonNaN float16ToCommonNaN_sparc
+#define float16_add float16_add_sparc
 #define float16_default_nan float16_default_nan_sparc
 #define float16_is_quiet_nan float16_is_quiet_nan_sparc
 #define float16_is_signaling_nan float16_is_signaling_nan_sparc
 #define float16_maybe_silence_nan float16_maybe_silence_nan_sparc
 #define float16_squash_input_denormal float16_squash_input_denormal_sparc
+#define float16_sub float16_sub_sparc
 #define float16_to_float32 float16_to_float32_sparc
 #define float16_to_float64 float16_to_float64_sparc
 #define float32ToCommonNaN float32ToCommonNaN_sparc

qemu/sparc64.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_sparc64
 #define float128_unordered_quiet float128_unordered_quiet_sparc64
 #define float16ToCommonNaN float16ToCommonNaN_sparc64
+#define float16_add float16_add_sparc64
 #define float16_default_nan float16_default_nan_sparc64
 #define float16_is_quiet_nan float16_is_quiet_nan_sparc64
 #define float16_is_signaling_nan float16_is_signaling_nan_sparc64
 #define float16_maybe_silence_nan float16_maybe_silence_nan_sparc64
 #define float16_squash_input_denormal float16_squash_input_denormal_sparc64
+#define float16_sub float16_sub_sparc64
 #define float16_to_float32 float16_to_float32_sparc64
 #define float16_to_float64 float16_to_float64_sparc64
 #define float32ToCommonNaN float32ToCommonNaN_sparc64

qemu/x86_64.h

@@ -487,11 +487,13 @@
 #define float128_unordered float128_unordered_x86_64
 #define float128_unordered_quiet float128_unordered_quiet_x86_64
 #define float16ToCommonNaN float16ToCommonNaN_x86_64
+#define float16_add float16_add_x86_64
 #define float16_default_nan float16_default_nan_x86_64
 #define float16_is_quiet_nan float16_is_quiet_nan_x86_64
 #define float16_is_signaling_nan float16_is_signaling_nan_x86_64
 #define float16_maybe_silence_nan float16_maybe_silence_nan_x86_64
 #define float16_squash_input_denormal float16_squash_input_denormal_x86_64
+#define float16_sub float16_sub_x86_64
 #define float16_to_float32 float16_to_float32_x86_64
 #define float16_to_float64 float16_to_float64_x86_64
 #define float32ToCommonNaN float32ToCommonNaN_x86_64