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target/arm: Update MSR access to UAO

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Backports commit 9eeb7a1c9531cb3574bfe2c36eb7624802c3ec00 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:48:00 -04:00 committed by Lioncash
parent 0630e66b5a
commit 5b5050c6ca
4 changed files with 41 additions and 0 deletions
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6
qemu/target/arm/cpu.h
View File

@ -1138,6 +1138,7 @@ void pmu_init(ARMCPU *cpu);
#define PSTATE_IL (1U << 20) #define PSTATE_IL (1U << 20)
#define PSTATE_SS (1U << 21) #define PSTATE_SS (1U << 21)
#define PSTATE_PAN (1U << 22) #define PSTATE_PAN (1U << 22)
#define PSTATE_UAO (1U << 23)
#define PSTATE_V (1U << 28) #define PSTATE_V (1U << 28)
#define PSTATE_C (1U << 29) #define PSTATE_C (1U << 29)
#define PSTATE_Z (1U << 30) #define PSTATE_Z (1U << 30)
@ -3515,6 +3516,11 @@ static inline bool isar_feature_aa64_ats1e1(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2; return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >= 2;
} }
static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
}
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
{ {
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0; return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;

21
qemu/target/arm/helper.c
View File

@ -3966,6 +3966,24 @@ static const ARMCPRegInfo pan_reginfo = {
.readfn = aa64_pan_read, .writefn = aa64_pan_write .readfn = aa64_pan_read, .writefn = aa64_pan_write
}; };
static uint64_t aa64_uao_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
return env->pstate & PSTATE_UAO;
}
static void aa64_uao_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
env->pstate = (env->pstate & ~PSTATE_UAO) | (value & PSTATE_UAO);
}
static const ARMCPRegInfo uao_reginfo = {
.name = "UAO", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 4,
.type = ARM_CP_NO_RAW, .access = PL1_RW,
.readfn = aa64_uao_read, .writefn = aa64_uao_write
};
static CPAccessResult aa64_cacheop_access(CPUARMState *env, static CPAccessResult aa64_cacheop_access(CPUARMState *env,
const ARMCPRegInfo *ri, const ARMCPRegInfo *ri,
bool isread) bool isread)
@ -7435,6 +7453,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, ats1cp_reginfo); define_arm_cp_regs(cpu, ats1cp_reginfo);
} }
#endif #endif
if (cpu_isar_feature(aa64_uao, cpu)) {
define_one_arm_cp_reg(cpu, &uao_reginfo);
}
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) { if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu)) {
define_arm_cp_regs(cpu, vhe_reginfo); define_arm_cp_regs(cpu, vhe_reginfo);

3
qemu/target/arm/internals.h
View File

@ -1114,6 +1114,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
if (isar_feature_aa64_pan(id)) { if (isar_feature_aa64_pan(id)) {
valid |= PSTATE_PAN; valid |= PSTATE_PAN;
} }
if (isar_feature_aa64_uao(id)) {
valid |= PSTATE_UAO;
}
return valid; return valid;
} }

11
qemu/target/arm/translate-a64.c
View File

@ -1798,6 +1798,17 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
s->base.is_jmp = DISAS_NEXT; s->base.is_jmp = DISAS_NEXT;
break; break;
case 0x03: /* UAO */
if (!dc_isar_feature(aa64_uao, s) || s->current_el == 0) {
goto do_unallocated;
}
if (crm & 1) {
set_pstate_bits(s, PSTATE_UAO);
} else {
clear_pstate_bits(s, PSTATE_UAO);
}
break;
case 0x04: /* PAN */ case 0x04: /* PAN */
if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) { if (!dc_isar_feature(aa64_pan, s) || s->current_el == 0) {
goto do_unallocated; goto do_unallocated;