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target-arm: Fix IL bit reported for Thumb coprocessor traps

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All Thumb coprocessor instructions are 32 bits, so the IL
bit in the syndrome register should be set. Pass false to the
syn_* function's is_16bit argument rather than s->thumb
so we report the correct IL bit.

Backports commit 4df322593037d2700f72dfdfb967300b7ad2e696 from qemu
This commit is contained in:
Peter Maydell 2018-02-20 11:38:25 -05:00 committed by Lioncash
parent 814bffc1ee
commit 5b8ad0e2fc
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 4 deletions
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8
qemu/target-arm/translate.c
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@ -7314,19 +7314,19 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
case 14: case 14:
if (is64) { if (is64) {
syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
isread, s->thumb); isread, false);
} else { } else {
syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
rt, isread, s->thumb); rt, isread, false);
} }
break; break;
case 15: case 15:
if (is64) { if (is64) {
syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
isread, s->thumb); isread, false);
} else { } else {
syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
rt, isread, s->thumb); rt, isread, false);
} }
break; break;
default: default: