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target/mips: Add placeholder and invocation of decode_nanomips_opc()

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Add empty body and invocation of decode_nanomips_opc() if the bit
ISA_NANOMIPS32 is set in ctx->insn_flags.

Backports commit c533c0f4741be62501ef6c7f6ce77ffbfc2e4964 from qemu
This commit is contained in:
Aleksandar Markovic 2018-08-27 04:16:24 -04:00 committed by Lioncash
parent 2389a5468c
commit 5decf2e0ed
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 17 additions and 1 deletions
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18
qemu/target/mips/translate.c
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@ -16696,6 +16696,19 @@ enum {
NM_EVP = 0x01,
};
/*
*
* nanoMIPS decoding engine
*
*/
static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
{
return 2;
}
/* SmartMIPS extension to MIPS32 */
#if defined(TARGET_MIPS64)
@ -21568,7 +21581,10 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
}
is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
if (!(ctx->hflags & MIPS_HFLAG_M16)) {
if (ctx->insn_flags & ISA_NANOMIPS32) {
ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
insn_bytes = decode_nanomips_opc(env, ctx);
} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
insn_bytes = 4;
decode_opc(env, ctx, &need_patch, &patch_offset);