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target/mips: Add placeholder and invocation of decode_nanomips_opc()
Add empty body and invocation of decode_nanomips_opc() if the bit ISA_NANOMIPS32 is set in ctx->insn_flags. Backports commit c533c0f4741be62501ef6c7f6ce77ffbfc2e4964 from qemu
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@ -16696,6 +16696,19 @@ enum {
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NM_EVP = 0x01,
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NM_EVP = 0x01,
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};
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};
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/*
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*
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* nanoMIPS decoding engine
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*
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*/
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static int decode_nanomips_opc(CPUMIPSState *env, DisasContext *ctx)
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{
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return 2;
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}
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/* SmartMIPS extension to MIPS32 */
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/* SmartMIPS extension to MIPS32 */
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#if defined(TARGET_MIPS64)
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#if defined(TARGET_MIPS64)
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@ -21568,7 +21581,10 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
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}
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}
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is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
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is_slot = ctx->hflags & MIPS_HFLAG_BMASK;
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if (!(ctx->hflags & MIPS_HFLAG_M16)) {
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if (ctx->insn_flags & ISA_NANOMIPS32) {
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ctx->opcode = cpu_lduw_code(env, ctx->base.pc_next);
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insn_bytes = decode_nanomips_opc(env, ctx);
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} else if (!(ctx->hflags & MIPS_HFLAG_M16)) {
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ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
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ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
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insn_bytes = 4;
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insn_bytes = 4;
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decode_opc(env, ctx, &need_patch, &patch_offset);
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decode_opc(env, ctx, &need_patch, &patch_offset);
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