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target/arm: Implement FMLAL and FMLSL for aarch64

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Backports commit 0caa5af802ff622c854ff4ee2e2b8cdd135b4d73 from qemu
This commit is contained in:
Richard Henderson 2019-02-28 15:36:36 -05:00 committed by Lioncash
parent 5473c3603f
commit 625d3f3cfb
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GPG Key ID: 4E3C3CC1031BA9C7
2 changed files with 28 additions and 1 deletions
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5
qemu/target/arm/cpu.h
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@ -3385,6 +3385,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
}
static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
}
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
{
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;

24
qemu/target/arm/translate-a64.c
View File

@ -11021,6 +11021,8 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
/* Floating point op subgroup of C3.6.16. */
static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
/* For floating point ops, the U, size[1] and opcode bits
* together indicate the operation. size[0] indicates single
* or double.
@ -11078,9 +11080,29 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
if (!fp_access_check(s)) {
return;
}
handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
return;
case 0x1d: /* FMLAL */
case 0x3d: /* FMLSL */
case 0x59: /* FMLAL2 */
case 0x79: /* FMLSL2 */
if (size & 1 || !dc_isar_feature(aa64_fhm, s)) {
unallocated_encoding(s);
return;
}
if (fp_access_check(s)) {
int is_s = extract32(insn, 23, 1);
int is_2 = extract32(insn, 29, 1);
int data = (is_2 << 1) | is_s;
tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm), tcg_ctx->cpu_env,
is_q ? 16 : 8, vec_full_reg_size(s),
data, gen_helper_gvec_fmlal_a64);
}
return;
default:
unallocated_encoding(s);
return;