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target/riscv: Split gen_arith_imm into functional and temp

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The tcg_gen_fooi_tl functions have some immediate constant
folding built in, which match up with some of the riscv asm
builtin macros, like mv and not.

Backports commit 598aa1160c3d17ab9271daf1f69d093ebada3f25 from qemu
This commit is contained in:
Richard Henderson 2019-05-28 19:04:46 -04:00 committed by Lioncash
parent a62b4e5def
commit 68ce00ac2f
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GPG Key ID: 4E3C3CC1031BA9C7
2 changed files with 25 additions and 9 deletions
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14
qemu/target/riscv/insn_trans/trans_rvi.inc.c
View File

@ -231,7 +231,7 @@ static bool trans_sd(DisasContext *ctx, arg_sd *a)
static bool trans_addi(DisasContext *ctx, arg_addi *a)
{
return gen_arith_imm(ctx, a, &tcg_gen_add_tl);
return gen_arith_imm_fn(ctx, a, &tcg_gen_addi_tl);
}
static void gen_slt(TCGContext *tcg_ctx, TCGv ret, TCGv s1, TCGv s2)
@ -246,25 +246,25 @@ static void gen_sltu(TCGContext *tcg_ctx, TCGv ret, TCGv s1, TCGv s2)
static bool trans_slti(DisasContext *ctx, arg_slti *a)
{
return gen_arith_imm(ctx, a, &gen_slt);
return gen_arith_imm_tl(ctx, a, &gen_slt);
}
static bool trans_sltiu(DisasContext *ctx, arg_sltiu *a)
{
return gen_arith_imm(ctx, a, &gen_sltu);
return gen_arith_imm_tl(ctx, a, &gen_sltu);
}
static bool trans_xori(DisasContext *ctx, arg_xori *a)
{
return gen_arith_imm(ctx, a, &tcg_gen_xor_tl);
return gen_arith_imm_fn(ctx, a, &tcg_gen_xori_tl);
}
static bool trans_ori(DisasContext *ctx, arg_ori *a)
{
return gen_arith_imm(ctx, a, &tcg_gen_or_tl);
return gen_arith_imm_fn(ctx, a, &tcg_gen_ori_tl);
}
static bool trans_andi(DisasContext *ctx, arg_andi *a)
{
return gen_arith_imm(ctx, a, &tcg_gen_and_tl);
return gen_arith_imm_fn(ctx, a, &tcg_gen_andi_tl);
}
static bool trans_slli(DisasContext *ctx, arg_slli *a)
{
@ -374,7 +374,7 @@ static bool trans_and(DisasContext *ctx, arg_and *a)
#ifdef TARGET_RISCV64
static bool trans_addiw(DisasContext *ctx, arg_addiw *a)
{
return gen_arith_imm(ctx, a, &gen_addw);
return gen_arith_imm_tl(ctx, a, &gen_addw);
}
static bool trans_slliw(DisasContext *ctx, arg_slliw *a)

20
qemu/target/riscv/translate.c
View File

@ -590,8 +590,24 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
/* Include the auto-generated decoder for 32 bit insn */
#include "decode_insn32.inc.c"
static bool gen_arith_imm(DisasContext *ctx, arg_i *a,
void(*func)(TCGContext *, TCGv, TCGv, TCGv))
static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
void(*func)(TCGContext *, TCGv, TCGv, target_long))
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1;
source1 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, source1, a->rs1);
(*func)(tcg_ctx, source1, source1, a->imm);
gen_set_gpr(ctx, a->rd, source1);
tcg_temp_free(tcg_ctx, source1);
return true;
}
static bool gen_arith_imm_tl(DisasContext *ctx, arg_i *a,
void (*func)(TCGContext *, TCGv, TCGv, TCGv))
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
TCGv source1, source2;