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target/riscv: Set VS bits in mideleg for Hyp extension

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Backports commit 713d8363deb3774db14fb88a9fcd99687dcef114 from qemu
This commit is contained in:
Alistair Francis 2020-03-22 01:32:07 -04:00 committed by Lioncash
parent ebc7b9371f
commit 6aabd67ef8
1 changed files with 3 additions and 0 deletions
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3
qemu/target/riscv/csr.c
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@ -448,6 +448,9 @@ static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
{
env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
if (riscv_has_ext(env, RVH)) {
env->mideleg |= VS_MODE_INTERRUPTS;
}
return 0;
}