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target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX

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Writes to AdvSIMD registers flush the bits above 128.

Backports commit 263273bc988e677ebadeaf7d0e49f6792a112db5 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:56:06 -04:00 committed by Lioncash
parent 18e9c4805f
commit 6eb8472344
1 changed files with 1 additions and 0 deletions
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qemu/target/arm/translate-a64.c
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@ -7218,6 +7218,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_ctx, tcg_resl);
write_vec_element(s, tcg_resh, rd, 1, MO_64);
tcg_temp_free_i64(tcg_ctx, tcg_resh);
clear_vec_high(s, true, rd);
}
/* ZIP/UZP/TRN