From 6ec6c71d5047bdd34adcc81acbf4b6bd10a541ac Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 19 Nov 2019 12:28:49 -0500 Subject: [PATCH] target/arm: Use store_reg_from_load in thumb2 code This function already includes the test for an interworking write to PC from a load. Change the T32 LDM implementation to match the A32 LDM implementation. For LDM, the reordering of the tests does not change valid behaviour because the only case that differs is has rn == 15, which is UNPREDICTABLE. Backports commit 69be3e13764111737e1a7a13bb0c231e4d5be756 from qemu --- qemu/target/arm/translate.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index 29f212f9..5dcd5a5d 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -9907,13 +9907,11 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) /* Load. */ tmp = tcg_temp_new_i32(tcg_ctx); gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - if (i == 15) { - gen_bx_excret(s, tmp); - } else if (i == rn) { + if (i == rn) { loaded_var = tmp; loaded_base = 1; } else { - store_reg(s, i, tmp); + store_reg_from_load(s, i, tmp); } } else { /* Store. */ @@ -11054,11 +11052,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) tcg_temp_free_i32(tcg_ctx, addr); goto illegal_op; } - if (rs == 15) { - gen_bx_excret(s, tmp); - } else { - store_reg(s, rs, tmp); - } + store_reg_from_load(s, rs, tmp); } else { /* Store. */ tmp = load_reg(s, rs);