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https://github.com/yuzu-emu/unicorn.git
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target/arm: implement SHA-3 instructions
This implements emulation of the new SHA-3 instructions that have been added as an optional extensions to the ARMv8 Crypto Extensions in ARM v8.2. Backports commit cd270ade74ea86467f393a9fb9c54c4f1148c28f from qemu
This commit is contained in:
Ard Biesheuvel
Lioncash
parent
66b8b01f09
commit
72078a7674
@ -11742,62 +11742,6 @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn)
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tcg_temp_free_ptr(tcg_ctx, tcg_rn_ptr);
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}
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/* Crypto four-register
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* 31 23 22 21 20 16 15 14 10 9 5 4 0
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* ---------------------------------------------------
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* | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
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* ---------------------------------------------------
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*/
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static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int op0 = extract32(insn, 21, 2);
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int rm = extract32(insn, 16, 5);
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int ra = extract32(insn, 10, 5);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2];
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int pass;
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if (op0 > 1 || !arm_dc_feature(s, ARM_FEATURE_V8_SHA3)) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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tcg_op1 = tcg_temp_new_i64(tcg_ctx);
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tcg_op2 = tcg_temp_new_i64(tcg_ctx);
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tcg_op3 = tcg_temp_new_i64(tcg_ctx);
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tcg_res[0] = tcg_temp_new_i64(tcg_ctx);
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tcg_res[1] = tcg_temp_new_i64(tcg_ctx);
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for (pass = 0; pass < 2; pass++) {
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read_vec_element(s, tcg_op1, rn, pass, MO_64);
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read_vec_element(s, tcg_op2, rm, pass, MO_64);
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read_vec_element(s, tcg_op3, ra, pass, MO_64);
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if (op0 == 0) {
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/* EOR3 */
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tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_op2, tcg_op3);
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} else {
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/* BCAX */
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tcg_gen_andc_i64(tcg_ctx, tcg_res[pass], tcg_op2, tcg_op3);
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}
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tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_res[pass], tcg_op1);
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}
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write_vec_element(s, tcg_res[0], rd, 0, MO_64);
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write_vec_element(s, tcg_res[1], rd, 1, MO_64);
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tcg_temp_free(tcg_ctx, tcg_op1);
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tcg_temp_free(tcg_ctx, tcg_op2);
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tcg_temp_free(tcg_ctx, tcg_op3);
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tcg_temp_free(tcg_ctx, tcg_res[0]);
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tcg_temp_free(tcg_ctx, tcg_res[1]);
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}
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/* Crypto three-reg SHA512
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* 31 21 20 16 15 14 13 12 11 10 9 5 4 0
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* +-----------------------+------+---+---+-----+--------+------+------+
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@ -11930,6 +11874,124 @@ static void disas_crypto_two_reg_sha512(DisasContext *s, uint32_t insn)
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tcg_temp_free_ptr(tcg_ctx, tcg_rn_ptr);
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}
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/* Crypto four-register
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* 31 23 22 21 20 16 15 14 10 9 5 4 0
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* +-------------------+-----+------+---+------+------+------+
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* | 1 1 0 0 1 1 1 0 0 | Op0 | Rm | 0 | Ra | Rn | Rd |
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* +-------------------+-----+------+---+------+------+------+
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*/
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static void disas_crypto_four_reg(DisasContext *s, uint32_t insn)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int op0 = extract32(insn, 21, 2);
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int rm = extract32(insn, 16, 5);
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int ra = extract32(insn, 10, 5);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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int feature;
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switch (op0) {
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case 0: /* EOR3 */
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case 1: /* BCAX */
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feature = ARM_FEATURE_V8_SHA3;
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break;
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default:
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unallocated_encoding(s);
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return;
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}
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if (!arm_dc_feature(s, feature)) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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if (op0 < 2) {
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TCGv_i64 tcg_op1, tcg_op2, tcg_op3, tcg_res[2];
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int pass;
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tcg_op1 = tcg_temp_new_i64(tcg_ctx);
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tcg_op2 = tcg_temp_new_i64(tcg_ctx);
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tcg_op3 = tcg_temp_new_i64(tcg_ctx);
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tcg_res[0] = tcg_temp_new_i64(tcg_ctx);
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tcg_res[1] = tcg_temp_new_i64(tcg_ctx);
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for (pass = 0; pass < 2; pass++) {
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read_vec_element(s, tcg_op1, rn, pass, MO_64);
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read_vec_element(s, tcg_op2, rm, pass, MO_64);
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read_vec_element(s, tcg_op3, ra, pass, MO_64);
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if (op0 == 0) {
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/* EOR3 */
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tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_op2, tcg_op3);
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} else {
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/* BCAX */
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tcg_gen_andc_i64(tcg_ctx, tcg_res[pass], tcg_op2, tcg_op3);
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}
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tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_res[pass], tcg_op1);
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}
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write_vec_element(s, tcg_res[0], rd, 0, MO_64);
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write_vec_element(s, tcg_res[1], rd, 1, MO_64);
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tcg_temp_free_i64(tcg_ctx, tcg_op1);
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tcg_temp_free_i64(tcg_ctx, tcg_op2);
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tcg_temp_free_i64(tcg_ctx, tcg_op3);
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tcg_temp_free_i64(tcg_ctx, tcg_res[0]);
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tcg_temp_free_i64(tcg_ctx, tcg_res[1]);
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} else {
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g_assert_not_reached();
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}
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}
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/* Crypto XAR
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* 31 21 20 16 15 10 9 5 4 0
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* +-----------------------+------+--------+------+------+
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* | 1 1 0 0 1 1 1 0 1 0 0 | Rm | imm6 | Rn | Rd |
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* +-----------------------+------+--------+------+------+
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*/
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static void disas_crypto_xar(DisasContext *s, uint32_t insn)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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int rm = extract32(insn, 16, 5);
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int imm6 = extract32(insn, 10, 6);
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int rn = extract32(insn, 5, 5);
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int rd = extract32(insn, 0, 5);
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TCGv_i64 tcg_op1, tcg_op2, tcg_res[2];
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int pass;
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if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA3)) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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tcg_op1 = tcg_temp_new_i64(tcg_ctx);
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tcg_op2 = tcg_temp_new_i64(tcg_ctx);
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tcg_res[0] = tcg_temp_new_i64(tcg_ctx);
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tcg_res[1] = tcg_temp_new_i64(tcg_ctx);
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for (pass = 0; pass < 2; pass++) {
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read_vec_element(s, tcg_op1, rn, pass, MO_64);
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read_vec_element(s, tcg_op2, rm, pass, MO_64);
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tcg_gen_xor_i64(tcg_ctx, tcg_res[pass], tcg_op1, tcg_op2);
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tcg_gen_rotri_i64(tcg_ctx, tcg_res[pass], tcg_res[pass], imm6);
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}
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write_vec_element(s, tcg_res[0], rd, 0, MO_64);
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write_vec_element(s, tcg_res[1], rd, 1, MO_64);
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tcg_temp_free_i64(tcg_ctx, tcg_op1);
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tcg_temp_free_i64(tcg_ctx, tcg_op2);
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tcg_temp_free_i64(tcg_ctx, tcg_res[0]);
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tcg_temp_free_i64(tcg_ctx, tcg_res[1]);
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}
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/* C3.6 Data processing - SIMD, inc Crypto
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*
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* As the decode gets a little complex we are using a table based
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@ -11962,6 +12024,7 @@ static const AArch64DecodeTable data_proc_simd[] = {
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{ 0xce608000, 0xffe0b000, disas_crypto_three_reg_sha512 },
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{ 0xcec08000, 0xfffff000, disas_crypto_two_reg_sha512 },
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{ 0xce000000, 0xff808000, disas_crypto_four_reg },
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{ 0xce800000, 0xffe00000, disas_crypto_xar },
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{ 0x00000000, 0x00000000, NULL }
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};
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