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target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers

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Add the AArch64 registers MAIR_EL3 and TPIDR_EL3, which are the only
two which we had implemented the 32-bit Secure equivalents of but
not the 64-bit Secure versions.

Backports commit 4cfb8ad896a6f85953038bd913ce3d82d347013d from qemu
This commit is contained in:
Peter Maydell 2018-02-15 08:48:57 -05:00 committed by Lioncash
parent afaf2a99d3
commit 7d1422efc5
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 5 additions and 1 deletions
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6
qemu/target-arm/helper.c
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@ -871,6 +871,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
*/
{ "MAIR_EL1", 0,10,2, 3,0,0, ARM_CP_STATE_AA64,
0, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el[1]), },
{ "MAIR_EL3", 0,10,2, 3,6,0, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.mair_el[3]) },
/* For non-long-descriptor page tables these are PRRR and NMRR;
* regardless they still act as reads-as-written for QEMU.
*/
@ -2589,7 +2591,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
{ "CNTHP_CVAL_EL2", 0,14,2, 3,4,2, ARM_CP_STATE_AA64, ARM_CP_IO,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), {0, 0},
NULL, NULL, gt_hyp_cval_write, NULL, raw_write },
{ "CNTHP_CVAL", .15,0,14, 0,6,0, 0, ARM_CP_64BIT | ARM_CP_IO,
{ "CNTHP_CVAL", 15,0,14, 0,6,0, 0, ARM_CP_64BIT | ARM_CP_IO,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_HYP].cval), {0, 0},
NULL, NULL, gt_hyp_cval_write, NULL, raw_write },
{ "CNTHP_TVAL_EL2", 0,14,2, 3,4,0, ARM_CP_STATE_BOTH, ARM_CP_IO,
@ -2643,6 +2645,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
{ "CPTR_EL3", 0,1,1, 3,6,2, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.cptr_el[3]), {0, 0},
cptr_access },
{ "TPIDR_EL3", 0,13,0, 3,6,2, ARM_CP_STATE_AA64, 0,
PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el[3]) },
REGINFO_SENTINEL
};