From 7d930e8515bb8064a9af2417c120848600d36a7d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 15 Jun 2018 13:10:26 -0400 Subject: [PATCH] target/arm: Implement SVE reverse within elements Backports commit dae8fb9019d2aa6ccb151a19871df40de6c98e29 from qemu --- qemu/aarch64.h | 10 ++++++++ qemu/aarch64eb.h | 10 ++++++++ qemu/header_gen.py | 10 ++++++++ qemu/target/arm/helper-sve.h | 14 +++++++++++ qemu/target/arm/sve.decode | 7 ++++++ qemu/target/arm/sve_helper.c | 41 +++++++++++++++++++++++++++------ qemu/target/arm/translate-sve.c | 38 ++++++++++++++++++++++++++++++ 7 files changed, 123 insertions(+), 7 deletions(-) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 6ec5571f..4fcbc68c 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3444,11 +3444,21 @@ #define helper_sve_predtest helper_sve_predtest_aarch64 #define helper_sve_predtest1 helper_sve_predtest1_aarch64 #define helper_sve_punpk_p helper_sve_punpk_p_aarch64 +#define helper_sve_rbit_b helper_sve_rbit_b_aarch64 +#define helper_sve_rbit_d helper_sve_rbit_d_aarch64 +#define helper_sve_rbit_h helper_sve_rbit_h_aarch64 +#define helper_sve_rbit_s helper_sve_rbit_s_aarch64 #define helper_sve_rev_b helper_sve_rev_b_aarch64 #define helper_sve_rev_d helper_sve_rev_d_aarch64 #define helper_sve_rev_h helper_sve_rev_h_aarch64 #define helper_sve_rev_p helper_sve_rev_p_aarch64 #define helper_sve_rev_s helper_sve_rev_s_aarch64 +#define helper_sve_revb_h helper_sve_revb_h_aarch64 +#define helper_sve_revb_d helper_sve_revb_d_aarch64 +#define helper_sve_revb_s helper_sve_revb_s_aarch64 +#define helper_sve_revh_d helper_sve_revh_d_aarch64 +#define helper_sve_revh_s helper_sve_revh_s_aarch64 +#define helper_sve_revw_d helper_sve_revw_d_aarch64 #define helper_sve_sabd_zpzz_b helper_sve_sabd_zpzz_b_aarch64 #define helper_sve_sabd_zpzz_d helper_sve_sabd_zpzz_d_aarch64 #define helper_sve_sabd_zpzz_h helper_sve_sabd_zpzz_h_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 923666c0..aefc599e 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3444,11 +3444,21 @@ #define helper_sve_predtest helper_sve_predtest_aarch64eb #define helper_sve_predtest1 helper_sve_predtest1_aarch64eb #define helper_sve_punpk_p helper_sve_punpk_p_aarch64eb +#define helper_sve_rbit_b helper_sve_rbit_b_aarch64eb +#define helper_sve_rbit_d helper_sve_rbit_d_aarch64eb +#define helper_sve_rbit_h helper_sve_rbit_h_aarch64eb +#define helper_sve_rbit_s helper_sve_rbit_s_aarch64eb #define helper_sve_rev_b helper_sve_rev_b_aarch64eb #define helper_sve_rev_d helper_sve_rev_d_aarch64eb #define helper_sve_rev_h helper_sve_rev_h_aarch64eb #define helper_sve_rev_p helper_sve_rev_p_aarch64eb #define helper_sve_rev_s helper_sve_rev_s_aarch64eb +#define helper_sve_revb_h helper_sve_revb_h_aarch64eb +#define helper_sve_revb_d helper_sve_revb_d_aarch64eb +#define helper_sve_revb_s helper_sve_revb_s_aarch64eb +#define helper_sve_revh_d helper_sve_revh_d_aarch64eb +#define helper_sve_revh_s helper_sve_revh_s_aarch64eb +#define helper_sve_revw_d helper_sve_revw_d_aarch64eb #define helper_sve_sabd_zpzz_b helper_sve_sabd_zpzz_b_aarch64eb #define helper_sve_sabd_zpzz_d helper_sve_sabd_zpzz_d_aarch64eb #define helper_sve_sabd_zpzz_h helper_sve_sabd_zpzz_h_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index fcd3ad1f..7e2c4556 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3465,11 +3465,21 @@ aarch64_symbols = ( 'helper_sve_predtest', 'helper_sve_predtest1', 'helper_sve_punpk_p', + 'helper_sve_rbit_b', + 'helper_sve_rbit_d', + 'helper_sve_rbit_h', + 'helper_sve_rbit_s', 'helper_sve_rev_b', 'helper_sve_rev_d', 'helper_sve_rev_h', 'helper_sve_rev_p', 'helper_sve_rev_s', + 'helper_sve_revb_h', + 'helper_sve_revb_d', + 'helper_sve_revb_s', + 'helper_sve_revh_d', + 'helper_sve_revh_s', + 'helper_sve_revw_d', 'helper_sve_sabd_zpzz_b', 'helper_sve_sabd_zpzz_d', 'helper_sve_sabd_zpzz_h', diff --git a/qemu/target/arm/helper-sve.h b/qemu/target/arm/helper-sve.h index a58fb4ba..3b7c5490 100644 --- a/qemu/target/arm/helper-sve.h +++ b/qemu/target/arm/helper-sve.h @@ -465,6 +465,20 @@ DEF_HELPER_FLAGS_4(sve_compact_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_2(sve_last_active_element, TCG_CALL_NO_RWG, s32, ptr, i32) +DEF_HELPER_FLAGS_4(sve_revb_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_revb_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_revb_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_revh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_revh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_revw_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve_rbit_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_rbit_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_rbit_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve_rbit_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) diff --git a/qemu/target/arm/sve.decode b/qemu/target/arm/sve.decode index baaf2b80..c2c78dbb 100644 --- a/qemu/target/arm/sve.decode +++ b/qemu/target/arm/sve.decode @@ -456,6 +456,13 @@ CPY_m_v 00000101 .. 100000 100 ... ..... ..... @rd_pg_rn # SVE copy element from general register to vector (predicated) CPY_m_r 00000101 .. 101000 101 ... ..... ..... @rd_pg_rn +# SVE reverse within elements +# Note esz >= operation size +REVB 00000101 .. 1001 00 100 ... ..... ..... @rd_pg_rn +REVH 00000101 .. 1001 01 100 ... ..... ..... @rd_pg_rn +REVW 00000101 .. 1001 10 100 ... ..... ..... @rd_pg_rn +RBIT 00000101 .. 1001 11 100 ... ..... ..... @rd_pg_rn + ### SVE Predicate Logical Operations Group # SVE predicate logical operations diff --git a/qemu/target/arm/sve_helper.c b/qemu/target/arm/sve_helper.c index 8220013f..d9de00ff 100644 --- a/qemu/target/arm/sve_helper.c +++ b/qemu/target/arm/sve_helper.c @@ -237,6 +237,26 @@ static inline uint64_t expand_pred_s(uint8_t byte) return word[byte & 0x11]; } +/* Swap 16-bit words within a 32-bit word. */ +static inline uint32_t hswap32(uint32_t h) +{ + return rol32(h, 16); +} + +/* Swap 16-bit words within a 64-bit word. */ +static inline uint64_t hswap64(uint64_t h) +{ + uint64_t m = 0x0000ffff0000ffffull; + h = rol64(h, 32); + return ((h & m) << 16) | ((h >> 16) & m); +} + +/* Swap 32-bit words within a 64-bit word. */ +static inline uint64_t wswap64(uint64_t h) +{ + return rol64(h, 32); +} + #define LOGICAL_PPPP(NAME, FUNC) \ void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ { \ @@ -615,6 +635,20 @@ DO_ZPZ(sve_neg_h, uint16_t, H1_2, DO_NEG) DO_ZPZ(sve_neg_s, uint32_t, H1_4, DO_NEG) DO_ZPZ_D(sve_neg_d, uint64_t, DO_NEG) +DO_ZPZ(sve_revb_h, uint16_t, H1_2, bswap16) +DO_ZPZ(sve_revb_s, uint32_t, H1_4, bswap32) +DO_ZPZ_D(sve_revb_d, uint64_t, bswap64) + +DO_ZPZ(sve_revh_s, uint32_t, H1_4, hswap32) +DO_ZPZ_D(sve_revh_d, uint64_t, hswap64) + +DO_ZPZ_D(sve_revw_d, uint64_t, wswap64) + +DO_ZPZ(sve_rbit_b, uint8_t, H1, revbit8) +DO_ZPZ(sve_rbit_h, uint16_t, H1_2, revbit16) +DO_ZPZ(sve_rbit_s, uint32_t, H1_4, revbit32) +DO_ZPZ_D(sve_rbit_d, uint64_t, revbit64) + /* Three-operand expander, unpredicated, in which the third operand is "wide". */ #define DO_ZZW(NAME, TYPE, TYPEW, H, OP) \ @@ -1586,13 +1620,6 @@ void HELPER(sve_rev_b)(void *vd, void *vn, uint32_t desc) } } -static inline uint64_t hswap64(uint64_t h) -{ - uint64_t m = 0x0000ffff0000ffffull; - h = rol64(h, 32); - return ((h & m) << 16) | ((h >> 16) & m); -} - void HELPER(sve_rev_h)(void *vd, void *vn, uint32_t desc) { intptr_t i, j, opr_sz = simd_oprsz(desc); diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index eefe90d4..33e62490 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -2744,6 +2744,44 @@ static bool trans_CPY_m_v(DisasContext *s, arg_rpr_esz *a, uint32_t insn) return true; } +static bool trans_REVB(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] = { + NULL, + gen_helper_sve_revb_h, + gen_helper_sve_revb_s, + gen_helper_sve_revb_d, + }; + return do_zpz_ool(s, a, fns[a->esz]); +} + +static bool trans_REVH(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] = { + NULL, + NULL, + gen_helper_sve_revh_s, + gen_helper_sve_revh_d, + }; + return do_zpz_ool(s, a, fns[a->esz]); +} + +static bool trans_REVW(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + return do_zpz_ool(s, a, a->esz == 3 ? gen_helper_sve_revw_d : NULL); +} + +static bool trans_RBIT(DisasContext *s, arg_rpr_esz *a, uint32_t insn) +{ + static gen_helper_gvec_3 * const fns[4] = { + gen_helper_sve_rbit_b, + gen_helper_sve_rbit_h, + gen_helper_sve_rbit_s, + gen_helper_sve_rbit_d, + }; + return do_zpz_ool(s, a, fns[a->esz]); +} + /* *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */