From 8429d98b4094ce9a45f255517fb2064d8c431493 Mon Sep 17 00:00:00 2001 From: Craig Janeczek Date: Sun, 11 Nov 2018 05:52:14 -0500 Subject: [PATCH] target/mips: Define a bit for MXU in insn_flags Define a bit for MXU in insn_flags. This is the first non-MIPS (third party) ASE supported in QEMU for MIPS, so it is placed in the section "bits 56-63: vendor-specific ASEs". Backports commit a031ac61619294ae473a78d1834e757fad8b59e5 from qemu --- qemu/target/mips/mips-defs.h | 1 + 1 file changed, 1 insertion(+) diff --git a/qemu/target/mips/mips-defs.h b/qemu/target/mips/mips-defs.h index 4ebfaeb3..78c3973e 100644 --- a/qemu/target/mips/mips-defs.h +++ b/qemu/target/mips/mips-defs.h @@ -65,6 +65,7 @@ * bits 56-63: vendor-specific ASEs */ #define ASE_MMI 0x0100000000000000ULL +#define ASE_MXU 0x0200000000000000ULL /* MIPS CPU defines. */ #define CPU_MIPS1 (ISA_MIPS1)