target/riscv: vmfirst find-first-set mask bit

Backports 0db67e1c0c49011eb09c4f5b790eef15a2b4c351

qemu/header_gen.py

@@ -7259,6 +7259,7 @@ riscv_symbols = (
     'helper_vmornot_mm',
     'helper_vmxnor_mm',
     'helper_vmpopc_m',
+    'helper_vmfirst_m',
     'pmp_hart_has_privs',
     'pmpaddr_csr_read',
     'pmpaddr_csr_write',

qemu/riscv32.h

@@ -4695,6 +4695,7 @@
 #define helper_vmornot_mm helper_vmornot_mm_riscv32
 #define helper_vmxnor_mm helper_vmxnor_mm_riscv32
 #define helper_vmpopc_m helper_vmpopc_m_riscv32
+#define helper_vmfirst_m helper_vmfirst_m_riscv32
 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32
 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32
 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32

qemu/riscv64.h

@@ -4695,6 +4695,7 @@
 #define helper_vmornot_mm helper_vmornot_mm_riscv64
 #define helper_vmxnor_mm helper_vmxnor_mm_riscv64
 #define helper_vmpopc_m helper_vmpopc_m_riscv64
+#define helper_vmfirst_m helper_vmfirst_m_riscv64
 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64
 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64
 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64

qemu/target/riscv/helper.h

@@ -1106,3 +1106,5 @@ DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32)
 
 DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32)
+
+DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)

qemu/target/riscv/insn32.decode

@@ -556,6 +556,7 @@ vmnor_mm        011110 - ..... ..... 010 ..... 1010111 @r
 vmornot_mm      011100 - ..... ..... 010 ..... 1010111 @r
 vmxnor_mm       011111 - ..... ..... 010 ..... 1010111 @r
 vmpopc_m        010100 . ..... ----- 010 ..... 1010111 @r2_vm
+vmfirst_m       010101 . ..... ----- 010 ..... 1010111 @r2_vm
 
 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r

qemu/target/riscv/insn_trans/trans_rvv.inc.c

@@ -2461,3 +2461,37 @@ static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a)
     }
     return false;
 }
+
+/* vmfirst find-first-set mask bit */
+static bool trans_vmfirst_m(DisasContext *s, arg_rmr *a)
+{
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+
+    if (vext_check_isa_ill(s)) {
+        TCGv_ptr src2, mask;
+        TCGv dst;
+        TCGv_i32 desc;
+        uint32_t data = 0;
+        data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
+        data = FIELD_DP32(data, VDATA, VM, a->vm);
+        data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
+
+        mask = tcg_temp_new_ptr(tcg_ctx);
+        src2 = tcg_temp_new_ptr(tcg_ctx);
+        dst = tcg_temp_new(tcg_ctx);
+        desc = tcg_const_i32(tcg_ctx, simd_desc(0, s->vlen / 8, data));
+
+        tcg_gen_addi_ptr(tcg_ctx, src2, tcg_ctx->cpu_env, vreg_ofs(s, a->rs2));
+        tcg_gen_addi_ptr(tcg_ctx, mask, tcg_ctx->cpu_env, vreg_ofs(s, 0));
+
+        gen_helper_vmfirst_m(tcg_ctx, dst, mask, src2, tcg_ctx->cpu_env, desc);
+        gen_set_gpr(s, a->rd, dst);
+
+        tcg_temp_free_ptr(tcg_ctx, mask);
+        tcg_temp_free_ptr(tcg_ctx, src2);
+        tcg_temp_free(tcg_ctx, dst);
+        tcg_temp_free_i32(tcg_ctx, desc);
+        return true;
+    }
+    return false;
+}

qemu/target/riscv/vector_helper.c

@@ -4538,3 +4538,22 @@ target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env,
     }
     return cnt;
 }
+
+/* vmfirst find-first-set mask bit*/
+target_ulong HELPER(vmfirst_m)(void *v0, void *vs2, CPURISCVState *env,
+                               uint32_t desc)
+{
+    uint32_t mlen = vext_mlen(desc);
+    uint32_t vm = vext_vm(desc);
+    uint32_t vl = env->vl;
+    int i;
+
+    for (i = 0; i < vl; i++) {
+        if (vm || vext_elem_mask(v0, mlen, i)) {
+            if (vext_elem_mask(vs2, mlen, i)) {
+                return i;
+            }
+        }
+    }
+    return -1LL;
+}