mirror of
https://github.com/yuzu-emu/unicorn.git
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target/arm: Implement SVE Integer Wide Immediate - Predicated Group
Backports commit f25a2361539626721dbccce14c077cad03b2e72c from qemu
This commit is contained in:
parent
f4ecf1a152
commit
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@ -3338,6 +3338,14 @@
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#define helper_sve_cnt_zpz_d helper_sve_cnt_zpz_d_aarch64
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#define helper_sve_cnt_zpz_d helper_sve_cnt_zpz_d_aarch64
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#define helper_sve_cnt_zpz_h helper_sve_cnt_zpz_h_aarch64
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#define helper_sve_cnt_zpz_h helper_sve_cnt_zpz_h_aarch64
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#define helper_sve_cnt_zpz_s helper_sve_cnt_zpz_s_aarch64
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#define helper_sve_cnt_zpz_s helper_sve_cnt_zpz_s_aarch64
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#define helper_sve_cpy_m_b helper_sve_cpy_m_b_aarch64
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#define helper_sve_cpy_m_d helper_sve_cpy_m_d_aarch64
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#define helper_sve_cpy_m_h helper_sve_cpy_m_h_aarch64
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#define helper_sve_cpy_m_s helper_sve_cpy_m_s_aarch64
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#define helper_sve_cpy_z_b helper_sve_cpy_z_b_aarch64
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#define helper_sve_cpy_z_d helper_sve_cpy_z_d_aarch64
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#define helper_sve_cpy_z_h helper_sve_cpy_z_h_aarch64
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#define helper_sve_cpy_z_s helper_sve_cpy_z_s_aarch64
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#define helper_sve_eor_pppp helper_sve_eor_pppp_aarch64
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#define helper_sve_eor_pppp helper_sve_eor_pppp_aarch64
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#define helper_sve_eor_zpzz_b helper_sve_eor_zpzz_b_aarch64
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#define helper_sve_eor_zpzz_b helper_sve_eor_zpzz_b_aarch64
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#define helper_sve_eor_zpzz_d helper_sve_eor_zpzz_d_aarch64
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#define helper_sve_eor_zpzz_d helper_sve_eor_zpzz_d_aarch64
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@ -3338,6 +3338,14 @@
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#define helper_sve_cnt_zpz_d helper_sve_cnt_zpz_d_aarch64eb
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#define helper_sve_cnt_zpz_d helper_sve_cnt_zpz_d_aarch64eb
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#define helper_sve_cnt_zpz_h helper_sve_cnt_zpz_h_aarch64eb
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#define helper_sve_cnt_zpz_h helper_sve_cnt_zpz_h_aarch64eb
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#define helper_sve_cnt_zpz_s helper_sve_cnt_zpz_s_aarch64eb
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#define helper_sve_cnt_zpz_s helper_sve_cnt_zpz_s_aarch64eb
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#define helper_sve_cpy_m_b helper_sve_cpy_m_b_aarch64eb
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#define helper_sve_cpy_m_d helper_sve_cpy_m_d_aarch64eb
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#define helper_sve_cpy_m_h helper_sve_cpy_m_h_aarch64eb
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#define helper_sve_cpy_m_s helper_sve_cpy_m_s_aarch64eb
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#define helper_sve_cpy_z_b helper_sve_cpy_z_b_aarch64eb
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#define helper_sve_cpy_z_d helper_sve_cpy_z_d_aarch64eb
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#define helper_sve_cpy_z_h helper_sve_cpy_z_h_aarch64eb
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#define helper_sve_cpy_z_s helper_sve_cpy_z_s_aarch64eb
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#define helper_sve_eor_pppp helper_sve_eor_pppp_aarch64eb
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#define helper_sve_eor_pppp helper_sve_eor_pppp_aarch64eb
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#define helper_sve_eor_zpzz_b helper_sve_eor_zpzz_b_aarch64eb
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#define helper_sve_eor_zpzz_b helper_sve_eor_zpzz_b_aarch64eb
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#define helper_sve_eor_zpzz_d helper_sve_eor_zpzz_d_aarch64eb
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#define helper_sve_eor_zpzz_d helper_sve_eor_zpzz_d_aarch64eb
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@ -3359,6 +3359,14 @@ aarch64_symbols = (
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'helper_sve_cnt_zpz_d',
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'helper_sve_cnt_zpz_d',
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'helper_sve_cnt_zpz_h',
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'helper_sve_cnt_zpz_h',
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'helper_sve_cnt_zpz_s',
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'helper_sve_cnt_zpz_s',
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'helper_sve_cpy_m_b',
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'helper_sve_cpy_m_d',
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'helper_sve_cpy_m_h',
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'helper_sve_cpy_m_s',
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'helper_sve_cpy_z_b',
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'helper_sve_cpy_z_d',
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'helper_sve_cpy_z_h',
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'helper_sve_cpy_z_s',
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'helper_sve_eor_pppp',
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'helper_sve_eor_pppp',
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'helper_sve_eor_zpzz_b',
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'helper_sve_eor_zpzz_b',
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'helper_sve_eor_zpzz_d',
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'helper_sve_eor_zpzz_d',
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@ -404,6 +404,16 @@ DEF_HELPER_FLAGS_4(sve_uqaddi_s, TCG_CALL_NO_RWG, void, ptr, ptr, s64, i32)
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DEF_HELPER_FLAGS_4(sve_uqaddi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(sve_uqaddi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(sve_uqsubi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(sve_uqsubi_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_5(sve_cpy_m_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_5(sve_cpy_m_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_5(sve_cpy_m_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_5(sve_cpy_m_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(sve_cpy_z_b, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(sve_cpy_z_h, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(sve_cpy_z_s, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_4(sve_cpy_z_d, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32)
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DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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@ -22,7 +22,7 @@
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###########################################################################
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###########################################################################
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# Named fields. These are primarily for disjoint fields.
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# Named fields. These are primarily for disjoint fields.
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%imm4_16_p1 16:4 !function=plus1
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%imm4_16_p1 16:4 !function=plus1
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%imm6_22_5 22:1 5:5
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%imm6_22_5 22:1 5:5
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%imm9_16_10 16:s6 10:3
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%imm9_16_10 16:s6 10:3
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@ -38,6 +38,9 @@
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%tszimm16_shr 22:2 16:5 !function=tszimm_shr
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%tszimm16_shr 22:2 16:5 !function=tszimm_shr
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%tszimm16_shl 22:2 16:5 !function=tszimm_shl
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%tszimm16_shl 22:2 16:5 !function=tszimm_shl
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# Signed 8-bit immediate, optionally shifted left by 8.
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%sh8_i8s 5:9 !function=expand_imm_sh8s
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# Either a copy of rd (at bit 0), or a different source
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# Either a copy of rd (at bit 0), or a different source
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# as propagated via the MOVPRFX instruction.
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# as propagated via the MOVPRFX instruction.
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%reg_movprfx 0:5
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%reg_movprfx 0:5
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@ -112,6 +115,11 @@
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@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
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@rd_rn_tszimm ........ .. ... ... ...... rn:5 rd:5 \
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&rri_esz esz=%tszimm16_esz
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&rri_esz esz=%tszimm16_esz
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# Two register operand, one immediate operand, with 4-bit predicate.
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# User must fill in imm.
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@rdn_pg4 ........ esz:2 .. pg:4 ... ........ rd:5 \
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&rpri_esz rn=%reg_movprfx
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# Two register operand, one encoded bitmask.
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# Two register operand, one encoded bitmask.
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@rdn_dbm ........ .. .... dbm:13 rd:5 \
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@rdn_dbm ........ .. .... dbm:13 rd:5 \
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&rr_dbm rn=%reg_movprfx
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&rr_dbm rn=%reg_movprfx
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@ -345,6 +353,15 @@ AND_zzi 00000101 10 0000 ............. ..... @rdn_dbm
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# SVE broadcast bitmask immediate
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# SVE broadcast bitmask immediate
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DUPM 00000101 11 0000 dbm:13 rd:5
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DUPM 00000101 11 0000 dbm:13 rd:5
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### SVE Integer Wide Immediate - Predicated Group
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# SVE copy floating-point immediate (predicated)
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FCPY 00000101 .. 01 .... 110 imm:8 ..... @rdn_pg4
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# SVE copy integer immediate (predicated)
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CPY_m_i 00000101 .. 01 .... 01 . ........ ..... @rdn_pg4 imm=%sh8_i8s
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CPY_z_i 00000101 .. 01 .... 00 . ........ ..... @rdn_pg4 imm=%sh8_i8s
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### SVE Predicate Logical Operations Group
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### SVE Predicate Logical Operations Group
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# SVE predicate logical operations
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# SVE predicate logical operations
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@ -1370,3 +1370,111 @@ void HELPER(sve_uqsubi_d)(void *d, void *a, uint64_t b, uint32_t desc)
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*(uint64_t *)(d + i) = (ai < b ? 0 : ai - b);
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*(uint64_t *)(d + i) = (ai < b ? 0 : ai - b);
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}
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}
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}
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}
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/* Two operand predicated copy immediate with merge. All valid immediates
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* can fit within 17 signed bits in the simd_data field.
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*/
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void HELPER(sve_cpy_m_b)(void *vd, void *vn, void *vg,
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uint64_t mm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd, *n = vn;
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uint8_t *pg = vg;
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mm = dup_const(MO_8, mm);
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for (i = 0; i < opr_sz; i += 1) {
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uint64_t nn = n[i];
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uint64_t pp = expand_pred_b(pg[H1(i)]);
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d[i] = (mm & pp) | (nn & ~pp);
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}
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}
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void HELPER(sve_cpy_m_h)(void *vd, void *vn, void *vg,
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uint64_t mm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd, *n = vn;
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uint8_t *pg = vg;
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mm = dup_const(MO_16, mm);
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for (i = 0; i < opr_sz; i += 1) {
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uint64_t nn = n[i];
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uint64_t pp = expand_pred_h(pg[H1(i)]);
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d[i] = (mm & pp) | (nn & ~pp);
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}
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}
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void HELPER(sve_cpy_m_s)(void *vd, void *vn, void *vg,
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uint64_t mm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd, *n = vn;
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uint8_t *pg = vg;
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mm = dup_const(MO_32, mm);
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for (i = 0; i < opr_sz; i += 1) {
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uint64_t nn = n[i];
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uint64_t pp = expand_pred_s(pg[H1(i)]);
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d[i] = (mm & pp) | (nn & ~pp);
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}
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}
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void HELPER(sve_cpy_m_d)(void *vd, void *vn, void *vg,
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uint64_t mm, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd, *n = vn;
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uint8_t *pg = vg;
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for (i = 0; i < opr_sz; i += 1) {
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uint64_t nn = n[i];
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d[i] = (pg[H1(i)] & 1 ? mm : nn);
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}
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}
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void HELPER(sve_cpy_z_b)(void *vd, void *vg, uint64_t val, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd;
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uint8_t *pg = vg;
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val = dup_const(MO_8, val);
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for (i = 0; i < opr_sz; i += 1) {
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d[i] = val & expand_pred_b(pg[H1(i)]);
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}
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}
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void HELPER(sve_cpy_z_h)(void *vd, void *vg, uint64_t val, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd;
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uint8_t *pg = vg;
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val = dup_const(MO_16, val);
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for (i = 0; i < opr_sz; i += 1) {
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d[i] = val & expand_pred_h(pg[H1(i)]);
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}
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}
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void HELPER(sve_cpy_z_s)(void *vd, void *vg, uint64_t val, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd;
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uint8_t *pg = vg;
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val = dup_const(MO_32, val);
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for (i = 0; i < opr_sz; i += 1) {
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d[i] = val & expand_pred_s(pg[H1(i)]);
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}
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}
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void HELPER(sve_cpy_z_d)(void *vd, void *vg, uint64_t val, uint32_t desc)
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{
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intptr_t i, opr_sz = simd_oprsz(desc) / 8;
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uint64_t *d = vd;
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uint8_t *pg = vg;
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for (i = 0; i < opr_sz; i += 1) {
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d[i] = (pg[H1(i)] & 1 ? val : 0);
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}
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}
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@ -59,6 +59,12 @@ static inline int plus1(int x)
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return x + 1;
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return x + 1;
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}
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}
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/* The SH bit is in bit 8. Extract the low 8 and shift. */
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static inline int expand_imm_sh8s(int x)
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{
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return (int8_t)x << (x & 0x100 ? 8 : 0);
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}
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/*
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/*
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* Include the generated decoder.
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* Include the generated decoder.
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*/
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*/
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@ -1904,6 +1910,92 @@ static bool trans_DUPM(DisasContext *s, arg_DUPM *a, uint32_t insn)
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return true;
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return true;
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}
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}
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/*
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*** SVE Integer Wide Immediate - Predicated Group
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*/
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/* Implement all merging copies. This is used for CPY (immediate),
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* FCPY, CPY (scalar), CPY (SIMD&FP scalar).
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*/
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static void do_cpy_m(DisasContext *s, int esz, int rd, int rn, int pg,
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TCGv_i64 val)
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{
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typedef void gen_cpy(TCGContext *, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32);
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static gen_cpy * const fns[4] = {
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gen_helper_sve_cpy_m_b, gen_helper_sve_cpy_m_h,
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gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d,
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};
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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unsigned vsz = vec_full_reg_size(s);
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TCGv_i32 desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, vsz, 0));
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TCGv_ptr t_zd = tcg_temp_new_ptr(tcg_ctx);
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TCGv_ptr t_zn = tcg_temp_new_ptr(tcg_ctx);
|
||||||
|
TCGv_ptr t_pg = tcg_temp_new_ptr(tcg_ctx);
|
||||||
|
|
||||||
|
tcg_gen_addi_ptr(tcg_ctx, t_zd, tcg_ctx->cpu_env, vec_full_reg_offset(s, rd));
|
||||||
|
tcg_gen_addi_ptr(tcg_ctx, t_zn, tcg_ctx->cpu_env, vec_full_reg_offset(s, rn));
|
||||||
|
tcg_gen_addi_ptr(tcg_ctx, t_pg, tcg_ctx->cpu_env, pred_full_reg_offset(s, pg));
|
||||||
|
|
||||||
|
fns[esz](tcg_ctx, t_zd, t_zn, t_pg, val, desc);
|
||||||
|
|
||||||
|
tcg_temp_free_ptr(tcg_ctx, t_zd);
|
||||||
|
tcg_temp_free_ptr(tcg_ctx, t_zn);
|
||||||
|
tcg_temp_free_ptr(tcg_ctx, t_pg);
|
||||||
|
tcg_temp_free_i32(tcg_ctx, desc);
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool trans_FCPY(DisasContext *s, arg_FCPY *a, uint32_t insn)
|
||||||
|
{
|
||||||
|
if (a->esz == 0) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
if (sve_access_check(s)) {
|
||||||
|
/* Decode the VFP immediate. */
|
||||||
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||||
|
uint64_t imm = vfp_expand_imm(a->esz, a->imm);
|
||||||
|
TCGv_i64 t_imm = tcg_const_i64(tcg_ctx, imm);
|
||||||
|
do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
|
||||||
|
tcg_temp_free_i64(tcg_ctx, t_imm);
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool trans_CPY_m_i(DisasContext *s, arg_rpri_esz *a, uint32_t insn)
|
||||||
|
{
|
||||||
|
if (a->esz == 0 && extract32(insn, 13, 1)) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
if (sve_access_check(s)) {
|
||||||
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||||
|
TCGv_i64 t_imm = tcg_const_i64(tcg_ctx, a->imm);
|
||||||
|
do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm);
|
||||||
|
tcg_temp_free_i64(tcg_ctx, t_imm);
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
|
static bool trans_CPY_z_i(DisasContext *s, arg_CPY_z_i *a, uint32_t insn)
|
||||||
|
{
|
||||||
|
static gen_helper_gvec_2i * const fns[4] = {
|
||||||
|
gen_helper_sve_cpy_z_b, gen_helper_sve_cpy_z_h,
|
||||||
|
gen_helper_sve_cpy_z_s, gen_helper_sve_cpy_z_d,
|
||||||
|
};
|
||||||
|
|
||||||
|
if (a->esz == 0 && extract32(insn, 13, 1)) {
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
if (sve_access_check(s)) {
|
||||||
|
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||||
|
unsigned vsz = vec_full_reg_size(s);
|
||||||
|
TCGv_i64 t_imm = tcg_const_i64(tcg_ctx, a->imm);
|
||||||
|
tcg_gen_gvec_2i_ool(tcg_ctx, vec_full_reg_offset(s, a->rd),
|
||||||
|
pred_full_reg_offset(s, a->pg),
|
||||||
|
t_imm, vsz, vsz, 0, fns[a->esz]);
|
||||||
|
tcg_temp_free_i64(tcg_ctx, t_imm);
|
||||||
|
}
|
||||||
|
return true;
|
||||||
|
}
|
||||||
|
|
||||||
/*
|
/*
|
||||||
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
|
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
|
||||||
*/
|
*/
|
||||||
|
Loading…
Reference in New Issue
Block a user