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target-arm: Use clz opcode

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Backports commit 7539a012f614b724426ac9360238f3281d928a3f from qemu
This commit is contained in:
Richard Henderson 2018-03-01 16:13:02 -05:00 committed by Lioncash
parent 9b2752b0a9
commit 9cde8bfc44
No known key found for this signature in database
GPG Key ID: 4E3C3CC1031BA9C7
20 changed files with 7 additions and 40 deletions
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1
qemu/aarch64.h
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@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_aarch64
#define gen_helper_clz32 gen_helper_clz32_aarch64
#define gen_helper_clz64 gen_helper_clz64_aarch64
#define gen_helper_clz_arm gen_helper_clz_arm_aarch64
#define gen_helper_cpsr_read gen_helper_cpsr_read_aarch64
#define gen_helper_cpsr_write gen_helper_cpsr_write_aarch64
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_aarch64

1
qemu/aarch64eb.h
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@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_aarch64eb
#define gen_helper_clz32 gen_helper_clz32_aarch64eb
#define gen_helper_clz64 gen_helper_clz64_aarch64eb
#define gen_helper_clz_arm gen_helper_clz_arm_aarch64eb
#define gen_helper_cpsr_read gen_helper_cpsr_read_aarch64eb
#define gen_helper_cpsr_write gen_helper_cpsr_write_aarch64eb
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_aarch64eb

1
qemu/arm.h
View File

@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_arm
#define gen_helper_clz32 gen_helper_clz32_arm
#define gen_helper_clz64 gen_helper_clz64_arm
#define gen_helper_clz_arm gen_helper_clz_arm_arm
#define gen_helper_cpsr_read gen_helper_cpsr_read_arm
#define gen_helper_cpsr_write gen_helper_cpsr_write_arm
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_arm

1
qemu/armeb.h
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@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_armeb
#define gen_helper_clz32 gen_helper_clz32_armeb
#define gen_helper_clz64 gen_helper_clz64_armeb
#define gen_helper_clz_arm gen_helper_clz_arm_armeb
#define gen_helper_cpsr_read gen_helper_cpsr_read_armeb
#define gen_helper_cpsr_write gen_helper_cpsr_write_armeb
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_armeb

1
qemu/header_gen.py
View File

@ -692,7 +692,6 @@ symbols = (
'gen_helper_clear_pstate_ss',
'gen_helper_clz32',
'gen_helper_clz64',
'gen_helper_clz_arm',
'gen_helper_cpsr_read',
'gen_helper_cpsr_write',
'gen_helper_cpsr_write_eret',

1
qemu/m68k.h
View File

@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_m68k
#define gen_helper_clz32 gen_helper_clz32_m68k
#define gen_helper_clz64 gen_helper_clz64_m68k
#define gen_helper_clz_arm gen_helper_clz_arm_m68k
#define gen_helper_cpsr_read gen_helper_cpsr_read_m68k
#define gen_helper_cpsr_write gen_helper_cpsr_write_m68k
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_m68k

1
qemu/mips.h
View File

@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_mips
#define gen_helper_clz32 gen_helper_clz32_mips
#define gen_helper_clz64 gen_helper_clz64_mips
#define gen_helper_clz_arm gen_helper_clz_arm_mips
#define gen_helper_cpsr_read gen_helper_cpsr_read_mips
#define gen_helper_cpsr_write gen_helper_cpsr_write_mips
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_mips

1
qemu/mips64.h
View File

@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_mips64
#define gen_helper_clz32 gen_helper_clz32_mips64
#define gen_helper_clz64 gen_helper_clz64_mips64
#define gen_helper_clz_arm gen_helper_clz_arm_mips64
#define gen_helper_cpsr_read gen_helper_cpsr_read_mips64
#define gen_helper_cpsr_write gen_helper_cpsr_write_mips64
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_mips64

1
qemu/mips64el.h
View File

@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_mips64el
#define gen_helper_clz32 gen_helper_clz32_mips64el
#define gen_helper_clz64 gen_helper_clz64_mips64el
#define gen_helper_clz_arm gen_helper_clz_arm_mips64el
#define gen_helper_cpsr_read gen_helper_cpsr_read_mips64el
#define gen_helper_cpsr_write gen_helper_cpsr_write_mips64el
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_mips64el

1
qemu/mipsel.h
View File

@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_mipsel
#define gen_helper_clz32 gen_helper_clz32_mipsel
#define gen_helper_clz64 gen_helper_clz64_mipsel
#define gen_helper_clz_arm gen_helper_clz_arm_mipsel
#define gen_helper_cpsr_read gen_helper_cpsr_read_mipsel
#define gen_helper_cpsr_write gen_helper_cpsr_write_mipsel
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_mipsel

1
qemu/powerpc.h
View File

@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_powerpc
#define gen_helper_clz32 gen_helper_clz32_powerpc
#define gen_helper_clz64 gen_helper_clz64_powerpc
#define gen_helper_clz_arm gen_helper_clz_arm_powerpc
#define gen_helper_cpsr_read gen_helper_cpsr_read_powerpc
#define gen_helper_cpsr_write gen_helper_cpsr_write_powerpc
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_powerpc

1
qemu/sparc.h
View File

@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_sparc
#define gen_helper_clz32 gen_helper_clz32_sparc
#define gen_helper_clz64 gen_helper_clz64_sparc
#define gen_helper_clz_arm gen_helper_clz_arm_sparc
#define gen_helper_cpsr_read gen_helper_cpsr_read_sparc
#define gen_helper_cpsr_write gen_helper_cpsr_write_sparc
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_sparc

1
qemu/sparc64.h
View File

@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_sparc64
#define gen_helper_clz32 gen_helper_clz32_sparc64
#define gen_helper_clz64 gen_helper_clz64_sparc64
#define gen_helper_clz_arm gen_helper_clz_arm_sparc64
#define gen_helper_cpsr_read gen_helper_cpsr_read_sparc64
#define gen_helper_cpsr_write gen_helper_cpsr_write_sparc64
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_sparc64

10
qemu/target-arm/helper-a64.c
View File

@ -52,11 +52,6 @@ int64_t HELPER(sdiv64)(int64_t num, int64_t den)
return num / den;
}
uint64_t HELPER(clz64)(uint64_t x)
{
return clz64(x);
}
uint64_t HELPER(cls64)(uint64_t x)
{
return clrsb64(x);
@ -67,11 +62,6 @@ uint32_t HELPER(cls32)(uint32_t x)
return clrsb32(x);
}
uint32_t HELPER(clz32)(uint32_t x)
{
return clz32(x);
}
uint64_t HELPER(rbit64)(uint64_t x)
{
return revbit64(x);

2
qemu/target-arm/helper-a64.h
View File

@ -18,10 +18,8 @@
*/
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
DEF_HELPER_FLAGS_1(clz64, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cls64, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cls32, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(clz32, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
DEF_HELPER_3(vfp_cmpes_a64, i64, f32, f32, ptr)

5
qemu/target-arm/helper.c
View File

@ -4973,11 +4973,6 @@ uint32_t HELPER(uxtb16)(uint32_t x)
return res;
}
uint32_t HELPER(clz_arm)(uint32_t x)
{
return clz32(x);
}
int32_t HELPER(sdiv)(int32_t num, int32_t den)
{
if (den == 0)

2
qemu/target-arm/helper.h
View File

@ -1,7 +1,5 @@
DEF_HELPER_4(uc_tracecode, void, i32, i32, ptr, i64)
DEF_HELPER_FLAGS_1(clz_arm, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(sxtb16, TCG_CALL_NO_RWG_SE, i32, i32)
DEF_HELPER_FLAGS_1(uxtb16, TCG_CALL_NO_RWG_SE, i32, i32)

8
qemu/target-arm/translate-a64.c
View File

@ -4025,11 +4025,11 @@ static void handle_clz(DisasContext *s, unsigned int sf,
tcg_rn = cpu_reg(s, rn);
if (sf) {
gen_helper_clz64(tcg_ctx, tcg_rd, tcg_rn);
tcg_gen_clzi_i64(tcg_ctx, tcg_rd, tcg_rn, 64);
} else {
TCGv_i32 tcg_tmp32 = tcg_temp_new_i32(tcg_ctx);
tcg_gen_extrl_i64_i32(tcg_ctx, tcg_tmp32, tcg_rn);
gen_helper_clz(tcg_ctx, tcg_tmp32, tcg_tmp32);
tcg_gen_clzi_i32(tcg_ctx, tcg_tmp32, tcg_tmp32, 32);
tcg_gen_extu_i32_i64(tcg_ctx, tcg_rd, tcg_tmp32);
tcg_temp_free_i32(tcg_ctx, tcg_tmp32);
}
@ -7713,7 +7713,7 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
switch (opcode) {
case 0x4: /* CLS, CLZ */
if (u) {
gen_helper_clz64(tcg_ctx, tcg_rd, tcg_rn);
tcg_gen_clzi_i64(tcg_ctx, tcg_rd, tcg_rn, 64);
} else {
gen_helper_cls64(tcg_ctx, tcg_rd, tcg_rn);
}
@ -10407,7 +10407,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
goto do_cmop;
case 0x4: /* CLS */
if (u) {
gen_helper_clz32(tcg_ctx, tcg_res, tcg_op);
tcg_gen_clzi_i32(tcg_ctx, tcg_res, tcg_op, 32);
} else {
gen_helper_cls32(tcg_ctx, tcg_res, tcg_op);
}

6
qemu/target-arm/translate.c
View File

@ -7187,7 +7187,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
switch (size) {
case 0: gen_helper_neon_clz_u8(tcg_ctx, tmp, tmp); break;
case 1: gen_helper_neon_clz_u16(tcg_ctx, tmp, tmp); break;
case 2: gen_helper_clz(tcg_ctx, tmp, tmp); break;
case 2: tcg_gen_clzi_i32(tcg_ctx, tmp, tmp, 32); break;
default: abort();
}
break;
@ -8378,7 +8378,7 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
ARCH(5);
rd = (insn >> 12) & 0xf;
tmp = load_reg(s, rm);
gen_helper_clz(tcg_ctx, tmp, tmp);
tcg_gen_clzi_i32(tcg_ctx, tmp, tmp, 32);
store_reg(s, rd, tmp);
} else {
goto illegal_op;
@ -10147,7 +10147,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
tcg_temp_free_i32(tcg_ctx, tmp2);
break;
case 0x18: /* clz */
gen_helper_clz(tcg_ctx, tmp, tmp);
tcg_gen_clzi_i32(tcg_ctx, tmp, tmp, 32);
break;
case 0x20:
case 0x21:

1
qemu/x86_64.h
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@ -686,7 +686,6 @@
#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_x86_64
#define gen_helper_clz32 gen_helper_clz32_x86_64
#define gen_helper_clz64 gen_helper_clz64_x86_64
#define gen_helper_clz_arm gen_helper_clz_arm_x86_64
#define gen_helper_cpsr_read gen_helper_cpsr_read_x86_64
#define gen_helper_cpsr_write gen_helper_cpsr_write_x86_64
#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_x86_64