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target/riscv: Make VSTIP and VSEIP read-only in hip

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Backports e89b631cf44d590dbd2c250358f4130f64b5d890
This commit is contained in:
Georg Kotheimer 2021-03-30 15:13:18 -04:00 committed by Lioncash
parent eb778614fb
commit a392976e77
1 changed files with 4 additions and 3 deletions
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7
qemu/target/riscv/csr.c
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@ -371,7 +371,8 @@ static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
static const target_ulong hip_writable_mask = MIP_VSSIP;
static const target_ulong hvip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
static const target_ulong vsip_writable_mask = MIP_VSSIP;
static const char valid_vm_1_10_32[16] = {
@ -915,9 +916,9 @@ static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask)
{
int ret = rmw_mip(env, 0, ret_value, new_value,
write_mask & hip_writable_mask);
write_mask & hvip_writable_mask);
*ret_value &= hip_writable_mask;
*ret_value &= hvip_writable_mask;
return ret;
}