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target-arm: Make the 64-bit version of VTCR do the migration

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Move the ALIAS tag from VTCR_EL2 to VTCR so that we migrate the
64-bit version, as is usual. (This has no particular effect now
unless the guest wrote to the high RES0 bits of VTCR_EL2.)
Add a comment about why it's OK that we don't have the various
accessor functions that the EL1 TCR regdefs do.

Backports commit bf06c1123a427fefc2cf9cf8019578eafc19eb6f from qemu
This commit is contained in:
Peter Maydell 2018-02-22 11:42:44 -05:00 committed by Lioncash
parent a93e873441
commit a632d1b96d
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GPG Key ID: 4E3C3CC1031BA9C7
1 changed files with 7 additions and 3 deletions
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10
qemu/target-arm/helper.c
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@ -3127,11 +3127,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
{ "TCR_EL2", 0,2,0, 3,4,2, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.tcr_el[2]), {0, 0},
NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset },
{ "VTCR", 15,2,1, 0,4,2, ARM_CP_STATE_AA32, 0,
{ "VTCR", 15,2,1, 0,4,2, ARM_CP_STATE_AA32, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vtcr_el2), {0, 0},
access_el3_aa32ns },
{ "VTCR_EL2", 0,2,1, 3,4,2, ARM_CP_STATE_AA64, ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vtcr_el2) },
{ "VTCR_EL2", 0,2,1, 3,4,2, ARM_CP_STATE_AA64, 0,
PL2_RW, 0, NULL, 0,
/* no .writefn needed as this can't cause an ASID change;
* no .raw_writefn or .resetfn needed as we never use mask/base_mask
*/
offsetof(CPUARMState, cp15.vtcr_el2) },
{ "VTTBR", 15,0,2, 0,6,0, ARM_CP_STATE_AA32, ARM_CP_64BIT | ARM_CP_ALIAS,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.vttbr_el2), {0, 0},
access_el3_aa32ns, NULL, vttbr_write },