diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c
index e4a13946..61743045 100644
--- a/qemu/target-arm/helper.c
+++ b/qemu/target-arm/helper.c
@@ -3097,8 +3097,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
       NULL, NULL, hcr_write },
     { "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64,
       ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) },
-    { "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64,
-      ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) },
+    { "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64, 0,
+      PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) },
     { "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_AA64,
       0, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) },
     { "SPSR_EL2", 0,4,0, 3,4,0, ARM_CP_STATE_AA64,
@@ -3268,8 +3268,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
       NULL, NULL, vmsa_tcr_el1_write, NULL, raw_write, vmsa_ttbcr_reset },
     { "ELR_EL3", 0,4,0, 3,6,1, ARM_CP_STATE_AA64,
       ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[3]) },
-    { "ESR_EL3", 0,5,2, 3,6,0, ARM_CP_STATE_AA64,
-      ARM_CP_ALIAS, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[3]) },
+    { "ESR_EL3", 0,5,2, 3,6,0, ARM_CP_STATE_AA64, 0,
+      PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[3]) },
     { "FAR_EL3", 0,6,0, 3,6,0, ARM_CP_STATE_AA64,
       0, PL3_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.far_el[3]) },
     { "SPSR_EL3", 0,4,0, 3,6,0, ARM_CP_STATE_AA64,